Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendment of claims 1-5 and 8 in the reply filed on March 11th, 2026, are acknowledged. Claims 1 and 8 have been amended. Claims 6-7 have been cancelled. Claims 1-5 and 8 are pending.
Action on merits of claims 1-5 and 8 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: substrate
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Sekine (US 2017/0250214, hereinafter as Seki ‘214) in view of Watanabe (US 2006/0071251, hereinafter as Wata ‘251).
Regarding Claim 1, Seki ‘214 teaches an image sensor (Fig. 1, (100); [0038]), comprising:
pixels arrayed (Fig. 1, (300); [0038]) on a substrate (200; [0038]); and
a data line (signal lines S1-S5; [0038]) that transmits a signal read from each of the pixels, wherein the pixel includes: a photodetector (600; [0038]); and an N-type switch thin film transistor (TFT (400); [0038]) between the photodetector (600) and the data line (see Fig. 1),
wherein the photodetector includes: a top electrode (Fig. 4, (650); [0040]); a bottom electrode (Fig. 4, (610); [0040]) between the top electrode (650) and the substrate (200);
an intrinsic amorphous silicon layer (630; [0041]) between the top electrode (650) and the bottom electrode (610); a P-type amorphous silicon layer (640; [0041]) between the top electrode (650) and the intrinsic amorphous silicon layer (630); and an N-type amorphous silicon (Fig. 4, (620); [0040]) layer between the intrinsic amorphous silicon layer (630) and the bottom electrode (610), wherein the switch thin film transistor includes:
an oxide semiconductor part (430; [0045]);
a drain electrode (440) connected to the data line (signal line Sm; see Fig. 2);
a source electrode (450; [0041]) connected to the bottom electrode (610); and
a gate electrode (410; [0041]) positioned between the oxide semiconductor part (430) and the substrate (200) to face the source electrode across the oxide semiconductor portion in a film thickness direction, wherein the top electrode (650; [0040]) is an anode electrode of the photodetector and the bottom electrode (610; [0040]) is a cathode electrode of the photodetector.
Thus, Seki ‘214 is shown to teach all the features of the claim with the exception of explicitly the features: “an overlap region where the gate electrode and the drain electrode overlap in a plan view is smaller than an overlap region where the gate electrode and the source electrode overlap in a plan view”.
Wata ‘251 teaches an overlap region where the gate electrode (Fig. 3, (117); [0029]) and the drain electrode (115a; [0037]) overlap in a plan view is smaller than an overlap region where the gate electrode (117) and the source electrode (115b; [0029]) overlap in a plan view (see Fig. 3). Examiner considers the source electrode (115a) is the drain electrode and the drain electrode (115b) is the source electrode.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Seki ‘214 by having an overlap region where the gate electrode and the drain electrode overlap in a plan view is smaller than an overlap region where the gate electrode and the source electrode overlap in a plan view for the purpose of improving the performance of the solid state image pickup apparatus (see para. [0037) as suggested by Wata ‘251.
Further, it has been held to be within the general skill of a worker in the art to select a n-type thin film transistor; and the photodetector operates in reverse bias where a voltage of the cathode electrode exceeds a voltage of the anode electrode, wherein, when the switch thin film transistor is turned on to read out a signal from the photodetector, a voltage of the source electrode is lower than or equal to a voltage of the drain electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see para. [0071] of US 2021/0174051 as evidence). A person of ordinary skills in the art is motivated to have a n-type thin film transistor the switching TFT; and the photodetector operates in reverse bias where a voltage of the cathode electrode exceeds a voltage of the anode electrode, wherein, when the switch thin film transistor is turned on to read out a signal from the photodetector, a voltage of the source electrode is lower than or equal to a voltage of the drain electrode when this improves the performance of the image sensor device.
Amended claim 1 contains functional limitations “the photodetector operates in reverse bias where a voltage of the cathode electrode exceeds a voltage of the anode electrode, wherein, when the switch thin film transistor is turned on to read out a signal from the photodetector, a voltage of the source electrode is lower than or equal to a voltage of the drain electrode” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “the photodetector operates in reverse bias where a voltage of the cathode electrode exceeds a voltage of the anode electrode, wherein, when the switch thin film transistor is turned on to read out a signal from the photodetector, a voltage of the source electrode is lower than or equal to a voltage of the drain electrode” is nothing else than the result achieved by the invention.
The applicant’s claim 1 does not distinguish over Seki ‘214 and Wata ‘251 references regardless of the functions allegedly performed by the claimed device, because only the device per se is relevant, not the recited function of the photodetector/ the switch thin film transistor operates. In reference to the claim language referring to the function of the photodetector/the switch thin film transistor, intended use and other types of functional language (such as operates in reverse bias where a voltage of the cathode electrode exceeds a voltage of the anode electrode and the switch thin film transistor is turned on to read out a signal from the photodetector, a voltage of the source electrode is lower than or equal to a voltage of the drain electrode) must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
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Fig. 4 (Seki ‘119)
Regarding Claim 2, Wata ‘251 teaches the gate electrode (117) does not overlap the drain electrode (115a) in a plan view, and wherein a portion of the gate electrode (117) overlaps the source electrode (115b) in a plan view (see Fig. 3).
Regarding Claim 3, Wata ‘251 teaches a drain electrode side edge of the gate electrode (117) is in a region between a source electrode side edge of the drain electrode (115a) and a drain electrode side edge of the source electrode (115b) (see Fig. 3).
Regarding Claim 4, Wata ‘251 teaches a drain electrode side edge of the gate electrode (117) matches a drain electrode side edge of the source electrode (115b) (see Fig. 3).
Further, it has been held to be within the general skill of a worker in the art to select a drain electrode side edge of the gate electrode matches a drain electrode side edge of the source electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a drain electrode side edge of the gate electrode matches a drain electrode side edge of the source electrode when this improves the performance of the image sensor device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Seki ‘119 and Wata ‘251 as applied to claim 1 above, and further in view of Chiu (US 2006/0170048, hereinafter as Chiu ‘048).
Regarding Claim 5, Seki ‘119 and Wata ‘251 are shown to teach all the features of the claim with the exception of explicitly the features: “the drain electrode side edge of the gate electrode is a straight line in a channel width direction of the oxide semiconductor part, and wherein the drain electrode-side edge of the source electrode is a straight line in the channel width direction of the oxide semiconductor part”.
Chiu ‘048 teaches the drain electrode side edge of the gate electrode (302) is a straight line in a channel width direction of the oxide semiconductor part, and wherein the drain electrode-side edge of the source electrode (322) is a straight line in the channel width direction of the oxide semiconductor part (see Fig. 2A) .
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Seki ‘214 and Wata ‘251 by having the drain electrode side edge of the gate electrode is a straight line in a channel width direction of the oxide semiconductor part, and wherein the drain electrode-side edge of the source electrode is a straight line in the channel width direction of the oxide semiconductor part in order to reduce Cgd capacitance (see para. [0027]) for improving the performance of the display device (see para. [0004]-[0005]) as suggested by Chiu ‘048.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Seki ‘119 and Wata ‘251 as applied to claim 1 above, and further in view of Sekine (US 2015/0123119, hereinafter as Seki ‘119).
Regarding Claim 8, Seki ‘214 teaches a region of the oxide semiconductor part (430) between the source electrode and the drain electrode (see Fig. 4).
Seki ‘119 and Wata ‘251 are shown to teach all the features of the claim with the exception of explicitly the features: “a region of the oxide semiconductor part is covered by an etch stop”.
Seki ‘119 teaches a region of the oxide semiconductor part (Fig. 1, (130); [0047]) between the source electrode (145; [0044]) and the drain electrode (140; [0044]) is covered by an etch stop (135; [0044]). Examiner considers the channel protection film (135; [0047]) is the etch stop.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Seki ‘214 and Wata ‘251 by having a region of the oxide semiconductor part is covered by an etch stop in order to suppress characteristic deterioration of the switching element (see para. [0014]) as suggested by Seki ‘119.
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Fig. 1 (Seki ‘119)
Response to Arguments
Applicant’s arguments with respect to claims 1-5 and 8, filed on March 11th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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