DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 3/4/2026. Claims 1-20 are pending in this application. Claims 16-20 are withdrawn.
Claims 1-15 are examined in this Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-6, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0084375) in view of Gao (US 2023/0025859).
Re claim 1, Lee teaches, under BRI, Figs. 1E-F & H, [0041, 0046, 0048, 0051, 0052, 0057, 0061, 062], a semiconductor chip, comprising:
-a semiconductor substrate (100);
-a pad insulating layer (315) disposed on the semiconductor substrate (100);
-a through electrode structure (TSV 200) that partially penetrates the semiconductor substrate (100) but does not penetrate the pad insulating layer (315);
-an insulating liner (TSV liner 210) that at least partially surrounds the through electrode structure (200);
-a sidewall (vertical part of 420) that penetrates the pad insulating layer (315), a part of the semiconductor substrate (100) and an outermost layer of the insulating liner (210), and includes a pad hole (defined between 420) formed therein; and
-a bonding pad structure (400) disposed on the pad insulating layer (315) and that fills the pad hole and contacts the through electrode structure (200).
PNG
media_image1.png
315
507
media_image1.png
Greyscale
PNG
media_image2.png
311
497
media_image2.png
Greyscale
Lee does not explicitly an insulating sidewall.
Gao teaches an insulating sidewall (insulation layer 222) (Figs. 2D & 2M, [0058]).
PNG
media_image3.png
523
383
media_image3.png
Greyscale
As taught by Gao, one of ordinary skill in the art would utilize & modify the above teaching into Lee to obtain an insulating sidewall as claimed, because it aids in improving electrical insulation and conductive performance of the TSV.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Gao in combination Lee due to above reason.
Re claim 2, in combination cited above, Gao teaches, Fig. 2M, the insulating sidewall (222) contacts the through electrode structure (215).
Re claim 4, Lee teaches, Figs. 1F, H, a width in a horizontal direction of the pad hole (defined between 420) is narrower than a width in the horizontal direction of the through electrode structure (200).
Re claim 5, Lee teaches, Fig. 1H, the bonding pad structure (400) partially penetrates the through electrode structure (200) and is partially surrounded by the through electrode structure (200) and the insulating liner (210).
Re claim 6, Lee teaches, Figs. 1F, H, the through electrode structure (200) includes a conductive plug (240); and a plug barrier layer (220) that at least partially surrounds the conductive plug (240).
Re claim 8, in combination cited above, Gao teaches, Figs. 2D, G & M, the insulating sidewall (222) contacts the plug barrier layer (206), and does not contact the conductive plug (214) (see also Lee’s Fig. 1F).
Re claim 9, in combination cited above, Gao teaches, Figs. 2D, G & M, the insulating sidewall (222) penetrates the plug barrier layer (206), is partially surround by the plug barrier layer (206), and contacts the conductive plug (214) (see also Lee’s Fig. 1H).
3. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Gao as applied to claims 1 & 6 above, and further in view of Yu et al. (US 2013/0119543).
The teachings of Lee have been discussed above.
Re claim 7, Lee/Gao does not explicitly teach the bonding pad structure partially penetrates the conductive plug.
Yu teaches, Figs. 1I-L, [0028, 0030, 0033], the bonding pad structure (134, 136) partially penetrates the conductive plug (114, 116, 120).
As taught by Yu, one of ordinary skill in the art would utilize & modify the above teaching into Lee to obtain the bonding pad structure partially penetrates the conductive plug as claimed, because it aids in achieving high quality TSV & enhancing reliability of stacked wafer connections.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination with Lee/Gao due to above reason.
4. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Gao as applied to claim 1 above, and further in view of Kawano (US 2005/0221601).
The teachings of Lee/Gao have been discussed above.
Re claim 10, Lee teaches, Figs. 1F, H, the bonding pad structure (400) includes a pillar portion (center of 440) disposed in a pad hole; and a pad portion (left right of 440) disposed on the pad insulating layer (315).
Lee/Gao does not explicitly teach wherein a side surface of the pad portion has an under-cut structure in which a lower portion thereof is recessed inward.
Kawano teaches, Fig. 3, [0068, 0115], a side surface of the pad portion (left right parts of 131, 133) has an under-cut structure (between 133 & 145) in which a lower portion thereof is recessed inward.
As taught by Kawano, one of ordinary skill in the art would utilize & modify the above teaching into Lee to obtain a side surface of the pad portion has an under-cut structure in which a lower portion thereof is recessed inward as claimed, because it aids in achieving desired shape/dimension of the pad portion and improving electrical characteristics of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kawano in combination with Lee due to above reason.
6. Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Gao (US 2023/0025859) and Misuhashi et al. (US 2013/0020468).
Re claim 11, Lee teaches, under BRI, Figs. 1E-F & H, [0041, 0046, 0051, 0057, 0061, 062], a semiconductor chip, comprising:
-a semiconductor substrate (100) that includes a first surface and a second surface opposite to each other;
-a pad insulating layer (315) disposed on the second surface of the semiconductor substrate (100);
-a through electrode structure (200) that partially penetrates the semiconductor substrate (100) but does not penetrate the pad insulating layer (315), wherein the through electrode structure (200) includes a conductive plug (240) and a plug barrier layer (220) that surrounds the conductive plug (240);
-an insulating liner (TVS liner 210) that at least partially surrounds the through electrode structure (200);
-a sidewall (vertical part of 420) that penetrates the semiconductor substrate (100), the pad insulating layer (315) and an outermost of the insulating liner (210), and includes a pad hole (defined between 420) formed therein; and
-a bonding pad structure (400) disposed in the pad hole and that partially and vertically overlaps the pad insulating layer (315) and partially penetrates the through electrode structure (200).
PNG
media_image2.png
311
497
media_image2.png
Greyscale
Lee does not explicitly an insulating sidewall.
Gao teaches an insulating sidewall (insulation layer 222) (Figs. 2D & 2M, [0058]).
PNG
media_image3.png
523
383
media_image3.png
Greyscale
As taught by Gao, one of ordinary skill in the art would utilize & modify the above teaching into Lee to obtain an insulating sidewall as claimed, because it aids in improving electrical insulation and conductive performance of the TSV.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Gao in combination Lee due to above reason.
Lee/Gao further teaches TVS structures [0003], but does not explicitly teach wherein the through electrode structure includes a first through electrode structure and a second through electrode structure, and
an upper surface of the first through electrode structure is vertically closer to the second surface of the semiconductor substrate than an upper surface of the second through electrode structure.
Misuhashi teaches, Fig. 2, [0072, 0073], the through electrode structure includes a first through electrode structure (left or center 23) and a second through electrode structure (right 23), and
an upper surface of the first through electrode structure (left or center 23) is vertically closer to the second surface (bottom surface of 2a) of the semiconductor substrate (consider 2a) than an upper surface of the second through electrode structure (right 23).
PNG
media_image4.png
390
372
media_image4.png
Greyscale
As taught by Misuhashi, one of ordinary skill in the art would utilize & modify the above teaching into Lee to obtain the through electrode structure includes a first through electrode structure and a second through electrode structure, and an upper surface of the first through electrode structure is vertically closer to the second surface of the semiconductor substrate than an upper surface of the second through electrode structure as claimed, because it aids facilitating the electrical interconnection within the formed device & improving the device function.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Misuhashi in combination with Lee/Gao due to above reason.
Re claim 12, in combination cited above, Lee teaches, Fig. 1H, the first through electrode structure (200) is partially penetrated by the insulating sidewall (of 420) (see Gao’s teaching), and the insulating sidewall (420) contacts the conductive plug (240) and is partially covered by the plug barrier layer (220) (see also Gao’s Fig. 2M).
Re claim 13, in combination cited above, Lee teaches, Fig. 1H, the second through electrode structure (200) is partially penetrated by the insulating sidewall (consider 420) (see Gao’s teaching), and the insulating sidewall contacts the conductive plug (240) and is partially covered by the plug barrier layer (220) (see also Gao’s Fig. 2M).
Re claim 14, in combination cited above, Lee teaches, Fig. 1F, the second through electrode structure (200) is not penetrated by the insulating sidewall (consider 420) (see Gao’s teaching), and the insulating sidewall (of 420) contacts the plug barrier layer (220) and is partially covered by the insulating liner (210).
Re claim 15, in combination cited above, Lee teaches, Figs. 1F, H, [0003], the bonding pad structure (400) includes:
a first bonding pad structure (400) that partially penetrates the first through electrode structure (200) and a second bonding pad structure (400) (based on backside bonding structures [0003]) that partially penetrates the second through electrode structure (200), wherein
each of the first bonding pad structure (400) and the second bonding pad structure (400) includes a pillar portion (center of 440) disposed in a pad hole, and a pad portion (left right of 440) disposed on the pad insulating layer (315) and integrally formed with the pillar portion (center of 440), and
Misuhari teaches, Fig. 2, a length in a vertical direction of the pillar portion of the first bonding pad structure (pillar under right 23) is less than a length in the vertical direction of the pillar portion of the second bonding pad structure (pillar under center or left 23).
Response to Arguments
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/17/26