DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-10 and 12-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Amendments to claim 3 in the Applicant’s Arguments dated 02/26/2026 overcome the objections of the Office Action mailed on 12/11/2025, therefore the claim objections of the Office Action mailed on 12/11/2025 are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-10, 12-13, 15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishikawa et al. (US 2019/0371807 A1, hereinafter Nishikawa ‘807).
PNG
media_image1.png
784
975
media_image1.png
Greyscale
With respect to Claim 1 Nishikawa ‘807 discloses a semiconductor device (Fig 1-29D), comprising:
a source structure (10, Fig 29D, Para [0157]) that includes a support source layer (118, Fig 29D, Para [0157]);
a gate stack structure (242/232 and 142/132, Fig 29D, Para [0119], hereinafter GSS) on the support source layer (118);
a memory channel structure (55, Fig 29D, Para [0142]) that penetrates through (55 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (118)(55 penetrating a portion of 118 disclosed in Fig 29D); and
a separation structure (76, Fig 29D, Para [0172]) that penetrates through (76 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (118) (76 penetrating a portion of 118 disclosed in Fig 29D),
wherein the support source layer (118) includes:
a first source part (first source part of 118 as shown in annotated Fig 29D of Nishikawa ‘807, hereinafter FSP) through which the memory channel structure (55) penetrates (55 penetrating through FSP shown in annotated Fig 29D of Nishikawa ‘807);
a second source part (second source part of 118 as shown in annotated Fig 29D of Nishikawa ‘807, hereinafter SSP) through which the separation structure (76) penetrates (76 penetrating through FSP shown in annotated Fig 29D of Nishikawa ‘807),
wherein a top surface (top surface of FSP shown in annotated Fig 29D of Nishikawa ‘807) of the first source part (FSP) is farther than a top surface (top surface of SSP shown in annotated Fig 29D of Nishikawa ‘807) of the second source part (SSP) from the gate stack structure (GSS)(annotated Fig 29D of Nishikawa ‘807 discloses top surface of FSP is farther than top surface of SSP to GSS), and
wherein the first source part (FSP) and the second source part (SSP) are integral portions (annotated Fig 29D of Nishikawa ‘807 discloses FSP and SSP as integral parts of 118) of the support source layer (118).
With respect to Claim 2 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 1, and Nishikawa ‘807 further discloses wherein a cross-sectional thickness (thickness of FSP as shown in cross section view of annotated Fig 29D of Nishikawa ‘807) of the first source part (FSP) is less than a cross-sectional thickness (thickness of SSP as shown in cross section view of annotated Fig 29D of Nishikawa ‘807) of the second source part (SSP)(annotated Fig 29D of Nishikawa ‘807 discloses thickness of FSP is less than the thickness of SSP).
With respect to Claim 3 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 1, wherein the gate stack structure (GSS) includes a connection dielectric pattern (12/117/123/124, Fig 29C, Para [0085-0086 and 0158], hereinafter CDP) in contact with (disclosed in Fig 29D) the support source layer (118),
wherein the connection dielectric pattern (CDP) includes:
a first dielectric part (first dielectric part of CDP is shown in annotated Fig 29D of Nishikawa ‘807, hereinafter FDP) through which the memory channel structure (55) penetrates (55 penetrating GSS disclosed in Fig 29D); and
a second dielectric part (second dielectric part of CDP is shown in annotated Fig 29D_2 of Nishikawa ‘807, hereinafter SDP) through which the separation structure (76) penetrates (76 penetrating SDP disclosed in annotated Fig 29D of Nishikawa ‘807),
wherein a bottom surface (bottom surface of FDP as shown in annotated Fig 29D of Nishikawa ’807) of the first dielectric part (FDP) is farther than a bottom surface (bottom surface of SDP as shown in annotated Fig 29D of Nishikawa ‘807) of the second dielectric part (SDP) from the gate stack structure (GSS)(annotated Fig 29D of Nishikawa ‘807 discloses bottom surface of FDP farther than a bottom surface of SDP from the gate structure GSS).
With respect to Claim 4 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 3, and Nishikawa ‘807 further discloses wherein a cross-sectional thickness (thickness of FDP as shown in cross section view of annotated Fig 29D of Nishikawa ‘807) of the first dielectric part (FDP) is greater than a cross-sectional thickness (thickness of SDP as shown in cross section view of annotated Fig 29D of Nishikawa ‘807) of the second dielectric part (SDP)(annotated Fig 29D of Nishikawa ‘807 discloses thickness of FDP is greater than thickness of SDP).
With respect to Claim 5 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 1, and Nishikawa ‘807 discloses further comprising a support structure (20, Fig 29A, Para [0132]) that penetrates through (disclosed in Fig 29C) the gate stack structure (GSS) and at least a portion of the support source layer (118)(Para [0144] disclose that 20 has the same structural elements as 58 (openings for 55) and Fig 14 discloses 20 is the same length as 58, therefore 20 will penetrates the source structure 10 in the manner of 58 (opening for 55) shown in Fig 29D),
wherein the support source layer (118) further includes a third source part (third source part of 118 as shown in annotated Fig 29D of Nishikawa ‘807, hereinafter TSP) through which the support structure (20) penetrates (Fig 14 discloses the source structure 10 extends through region 200 where structure 20 is present and as described above 20 is the same length as 55, therefore 20 penetrates through the TSP), and
wherein a top surface (top surface of TSP as shown in annotated Fig 29D of Nishikawa ‘807) of the third source part (TSP) is farther than the top surface (top surface of SSP as shown in annotated Fig 29D of Nishikawa ‘807) of the second source part (SSP) from the gate stack structure (GSS)(annotated Fig 29D of Nishikawa ‘807 discloses top surface of the third part TSP is farther than the top surface of the second source part SSP from the gate stack).
PNG
media_image2.png
641
884
media_image2.png
Greyscale
With respect to Claim 6 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 5, and Nishikawa ‘807 further discloses wherein the separation structure (76) includes:
a first separation part (first 76 as shown in annotated Fig 29B of Nishikawa ‘807) adjacent to the memory channel structure (55)(Fig 29B and 29D shows first 76 adjacent to item 58 which Fig 29D and 29B and Para [0131] disclose as the opening of the memory structure 55); and
a second separation part (second 76 as shown in annotated Fig 29B and Fig 29A of Nishikawa ‘807) adjacent to the support structure (20),
wherein the first separation part (first 76 as shown in annotated Fig 29D of Nishikawa ‘807) penetrates through the second source part (SSP)(annotated Fig 29D of Nishikawa ‘807 discloses first 76 penetrates SSP),
wherein the support source layer (118) further includes a fourth source part (fourth source part of 118 shown in annotated Fig 29A of Nishikawa ‘807, hereinafter 4SP) through which the second separation part penetrates (second 76 as shown in annotated Fig 29B and Fig 29A of Nishikawa ‘807)(annotated Fig 29A of Nishikawa ‘807 discloses second 76 penetrates 4SP of 118), and
wherein a top surface of the fourth source part (top surface of 4SP as shown in annotated Fig 29A of Nishikawa ‘807) is closer than the top surface of the first source part (top surface of the FSP) and the top surface of the third source part (top surface of TSP) to the gate stack structure (GSS)(annotated Fig 29D discloses top surface of 4SP is closer to the top surface of FSP and top surface of TSP).
With respect to Claim 9 Nishikawa ‘807 discloses all limitation of the semiconductor device of claim 1, and Nishikawa ‘807 further discloses wherein the source structure (10) further includes:
a base source layer (112, Fig 29D, Para [0076]); and
an intervening source layer between the base source layer (114, Fig 29D, Para [0157]) and the support source layer (116),
wherein the intervening source layer (114) is electrically connected to the memory channel structure (55)(Fig 29D and Para [0157] discloses 114 is electrically connected to memory channel structure 55).
PNG
media_image3.png
753
1099
media_image3.png
Greyscale
With respect to Claim 10 Nishikawa ‘807 discloses a semiconductor device (Fig 1-29D), comprising:
a source structure (10, Fig 29D, Para [0157]) that includes a support source layer (114, Fig 29D, Para [0157]);
a gate stack structure (242/232 and 142/132 and 12/117/123/124, Fig 29D, Para [0119] and Para [0085-0086 and 0158], hereinafter GSS) that includes a connection dielectric pattern (12/117/123/124, Fig 29D, Para [0085-0086 and 0158], hereinafter CDP) in contact (CDP in contact with 114 disclosed in Fig 29D) with the support source layer (114);
a memory channel structure (55, Fig 29D, Para [0142]) that penetrates through (55 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (114)(55 penetrating a portion of 114 disclosed in Fig 29D); and
a separation structure (76, Fig 29D, Para [0172]) that penetrates through (76 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (114) (76 penetrating a portion of 114 disclosed in Fig 29D),
wherein the support source layer (114) includes:
a first source part (first source part of 114 as shown in annotated Fig 29D of Nishikawa ‘807, hereinafter FSP) through which the memory channel structure (55) penetrates (55 penetrating through FSP shown in annotated Fig 29D of Nishikawa ‘807); and
a second source part (second source part of 114 as shown in annotated Fig 29D of Nishikawa ‘807, hereinafter SSP) through which the separation structure (76) penetrates (76 penetrating through FSP shown in annotated Fig 29D of Nishikawa ‘807),
wherein the connection dielectric pattern (CDP) includes:
a first dielectric part (first dielectric part of CDP is shown in annotated Fig 29D_3 of Nishikawa ‘807, hereinafter FDP) through which the memory channel structure (55) penetrates (55 penetrating FDP is shown in annotated Fig 29D_3 of Nishikawa ‘807); and
a second dielectric part (second dielectric part of CDP is shown in annotated Fig 29D_3 of Nishikawa ‘807, hereinafter SDP) through which the separation structure (76) penetrates (76 penetrating SDP (through parts 124 and upper parts of 123) is shown in annotated Fig 29D_3 of Nishikawa ‘807),
wherein the first source part (FSP) includes a first top surface (first top surface of FSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807) in contact (first top surface of FSP is in contact with the FDP as shown in annotated Fig 29D_3 of Nishikawa ‘807) with the first dielectric part (FDP),
wherein the second source part (SSP) includes a second top surface (second top surface of SSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807) in contact (second top surface of SSP is in contact with the SDP as shown in annotated Fig 29D_3 of Nishikawa ‘807) with the second dielectric part (SDP), and
wherein a level (level of first top surface of FSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807) of the first top surface (first top surface of FSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807) is different from a level (level of second top surface of SSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807) of the second top surface (second top surface of SSP as shown in Annotated Fig 29D_3 of Nishikawa ‘807)(annotated Fig 29D_3 of Nishikawa ‘807 discloses a level of the first top surface of FSP is different from a level of the second top surface of SSP).
With respect to Claim 12 Nishikawa ‘807 discloses all limitations of the semiconductor device of claim 10, and Nishikawa ‘807 discloses further comprising a support structure (20, Fig 29C, Para [0152]) that penetrates through the gate stack structure (GSS) and the support source layer (114)(Fig 29C discloses 20 penetrates through GSS and show that 20 as the same length as memory openings 58, therefore 20 penetrates 114 also),
wherein the support source layer (114) further includes a third source part (third source part as shown in annotated Fig 29D of Nishikawa ‘807_3, hereinafter TSP) through which the support structure (20) penetrates(Fig 14 discloses the source structure 10 extends through region 200 where structure 20 is present and as described above 20 is the same length as 55, therefore 20 penetrates through the TSP),
wherein the connection dielectric pattern (CDP) further includes a third dielectric part (third dielectric part of CDP is shown in annotated Fig 29D_3 of Nishikawa ‘807, hereinafter TDP) through which the support structure (20) penetrates (Fig 14 discloses the source structure 10 extends through region 200 where structure 20 is and therefore the third dielectric part of CDP will extend into region 200 and therefore 20 will penetrate TDP), and
wherein the third source part (TSP) includes a third top surface (third top surface of TSP shown in annotated Fig 29D_3 of Nishikawa ‘807) in contact with the third dielectric part (TDP)(annotated Fig 29D_3 of Nishikawa ‘807 discloses the third top surface of TSP in contact with the TDP).
With respect to Claim 13 Nishikawa ‘807 discloses all limitations of the semiconductor device of claim 12, and Nishikawa ‘807 discloses further wherein a level of the third top surface is different from the level of the second top surface (annotated Fig 29D_3 of Nishikawa 29D_3 discloses a level of the third top surface is different than the level of the second top surface).
With respect to Claim 15 Nishikawa ‘807 discloses all limitations of the semiconductor device of claim 12, and Nishikawa ‘807 discloses further wherein a level of the third top surface is different from the level of the first top surface (annotated Fig 29D_3 discloses the level of the third top surface is different from the level of the first top surface).
With respect to Claim 17 Nishikawa ‘807 discloses all limitations of the semiconductor device of claim 10, and Nishikawa ‘807 further discloses wherein a thickness of the first source part (a thickness of FSP as shown in annotated Fig 29D_3 of Nishikawa ‘807) is less than a thickness of the first dielectric part (thickness of FDP as shown in annotated Fig 29D_3 of Nishikawa ‘807)(annotated Fig 29D_3 of Nishikawa ‘807 discloses a thickness of FSP is less than a thickness of FDP).
With respect to Claim 18 Nishikawa ‘807 discloses all limitations of the semiconductor device of claim 17, and Nishikawa ‘807 further discloses wherein a thickness of the second source part (a thickness of SSP as shown in annotated Fig 29D_3 of Nishikawa ‘807) is greater than a thickness of the second dielectric part (thickness of SDP as shown in annotated Fig 29D_3 of Nishikawa ‘807)(annotated Fig 29D_3 of Nishikawa ‘807 discloses a thickness of SSP is greater than a thickness of SDP).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa ‘807 in view of Lee (US 2017/0338241 A1, hereinafter Lee ‘241) in view of the following arguments.
PNG
media_image4.png
784
955
media_image4.png
Greyscale
With respect to Claim 19 Nishikawa ‘807 discloses wherein the semiconductor device (Fig 1-29D) includes:
a source structure (10, Fig 29D, Para [0157]) that includes a support source layer (114, Fig 29D, Para [0157]);
a gate stack structure (242/232 and 142/132, Fig 29D, Para [0119], hereinafter GSS) that includes a connection dielectric pattern (12/117/123, Fig 29D, Para [0085-0086 and 0158], hereinafter CDP) in contact (CDP in contact with 114 disclosed in Fig 29D) with the support source layer (114);
a memory channel structure (55, Fig 29D, Para [0142]) that penetrates through (55 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (114)(55 penetrating a portion of 114 disclosed in Fig 29D); and
a separation structure (76, Fig 29D, Para [0172]) that penetrates through (76 penetrating GSS disclosed in Fig 29D) the gate stack structure (GSS) and at least a portion of the support source layer (114) (76 penetrating a portion of 114 disclosed in Fig 29D),
wherein the support source layer (114) includes:
a first source part (first source part of 114 as shown in annotated Fig 29D_2 of Nishikawa ‘807, hereinafter FSP) through which the memory channel structure (55) penetrates (55 penetrating through FSP shown in annotated Fig 29D_2 of Nishikawa ‘807);
a second source part (second source part of 114 as shown in annotated Fig 29D_2 of Nishikawa ‘807, hereinafter SSP) through which the separation structure (76) penetrates (76 penetrating through FSP shown in annotated Fig 29D_2 of Nishikawa ‘807),
wherein the connection dielectric pattern (CDP) includes:
a first dielectric part (first dielectric part of CDP is shown in annotated Fig 29D_2 of Nishikawa ‘807, hereinafter FDP) that is above and in contact with (annotated Fig 29D_2 of Nishikawa ;807 discloses first dielectric part of CDP is above and in contact with first source part) the first source part (FSP); and
a second dielectric part (second dielectric part of CDP is shown in annotated Fig 29D_2 of Nishikawa ‘807, hereinafter SDP) that is above and in contact with (annotated Fig 29D_2 of Nishikawa ;807 discloses second dielectric part of CDP is above and in contact with second source part) the second source part (SSP),
wherein a thickness (a thickness of FSP shown in annotated Fig 29D_2) of the first source part (FSP) is less than a thickness of the second source part (SSP)(annotated Fig 29D_2 of Nishikawa ‘807 discloses thickness of FSP is less than thickness of SSP), and
wherein a thickness (a thickness of FDP shown in annotated Fig 29D_2) of the first dielectric part (FDP) is greater than a thickness (a thickness of SDP shown in annotated Fig 29D_2) of the second dielectric part (SDP).
But Nishikawa ‘807 fails to explicitly disclose an electronic system, comprising: a main board; a semiconductor device on the main board; and a controller on the main board and electrically connected to the semiconductor device.
Nevertheless, in a related endeavor, (Fig 12-3 of Lee ‘241), Lee ‘241 teaches an electronic system (Fig 12-13), comprising: a main board (board of system 1210, Fig 13, Para [0141] discloses system 1210 is described in Fig 12 and Para [0138] discloses memory system as a memory card, one of ordinary skill in the art would recognize that the memory card would be a board); a semiconductor device (1212, Fig 13, Para [0141]) on the main board (board of system 1210); and a controller (1211, Fig 13, Para [0141]) on the main board (board of system 1210) and electrically connected to the semiconductor device (1212)(Fig 13 and Para [0138] disclose 1211 connected to 1212).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘241’s electronic system, comprising: a main board; a semiconductor device on the main board; and a controller on the main board and electrically connected to the semiconductor device into Nishikawa ‘807’s device. Nishikawa ‘807 teaches a memory device but does not teach how to incorporate that device into a working system. Lee ‘241 teaches incorporating a memory device into a working system. The ordinary artisan would have been motivated to modify Nishikawa ‘807 in the manner set forth above, at least, Lee ‘214 teaches, as disclosed in Para [0003] how to incorporate the memory device into an memory system and adding the system to the device increases the functionality and value of the end device.
As incorporated, the electronic system as taught by Lee ‘241 would be used with the memory device of Nishikawa ‘807 so that the memory device of Nishikawa ‘807 would be used as the memory device (1212 of Lee ‘241).
With respect to Claim 20 Nishikawa ‘807 as modified by Lee ‘241 discloses all limitations of the electronic system of claim 19, and Nishikawa ‘807 discloses further wherein a top surface (top surface of FSP as shown in annotated Fig 29D_2 of Nishikawa ‘807) of the first source part (FSP) is farther than a top surface (top surface of SSP as shown in annotated Fig 29D_2 of Nishikawa ‘807) of the second source part (SSP) from the gate stack structure (GSS)(annotated Fig 29D_2 discloses a top surface of FSP is farther than a top surface of SSP from the gate stack structure GSS).
Allowable Subject Matter
Claims 7-8, 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 7: Allowable subject matter has been indicated because the closest prior art of record, Nishikawa et al. (US 2019/0371807 A1) and Lee (US 2017/338241 A1), either alone or in combination, fails to teach or fairly suggest the feature: “the support source layer includes a connection surface that connects the top surface of the first source part to the top surface of the second source part, wherein the connection surface is inclined”.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 8: Allowable subject matter has been indicated because the closest prior art of record, Nishikawa et al. (US 2019/0371807 A1) and Lee (US 2017/338241 A1), either alone or in combination, fails to teach or fairly suggest the feature: “the connection surface has a level that rises in a direction from the top surface of the first source part to the top surface of the second source part”.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 14: Allowable subject matter has been indicated because the closest prior art of record, Nishikawa et al. (US 2019/0371807 A1) and Lee (US 2017/338241 A1), either alone or in combination, fails to teach or fairly suggest the feature: “wherein the level of the third top surface is the same as the level of the first top surface”.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 16: Allowable subject matter has been indicated because the closest prior art of record, Nishikawa et al. (US 2019/0371807 A1) and Lee (US 2017/338241 A1), either alone or in combination, fails to teach or fairly suggest the feature: “wherein the level of the third top surface is the same as the level of the second top surface”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights