DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1, Embodiment I, Figs. 1, claims 1-7 and 16-19, in the reply filed on February 26, 2026 is acknowledged. However, after inspection, claims 7, 17 and 18 do not belong with the elected species. Claim 7 belongs with non-elected Species 2, Fig. 8 (see paragraph 139, paragraphs 132-139). Claims 17 and 18, belong to embodiments where there are a plurality of semiconductor integrated circuit components and a plurality of passive components. Applicant is reminded that they chose Group, I, Species 1, Fig. 1, not Figs. 2A-2G, 3A-3G, 4-6, 7A-7K. These figures were not even mention in the election/restriction requirement mailed December 30, 2025. Figures 2A-2G, 3A-3G read on a method of manufacture and a modification to the method of manufacture of non-elected Group II. Figures 7A-7K read on a method of manufacturing an inductor component. Figures 4-6 disclose different views of the inductor component. The Examiner notes that this was an attempt to try to incorporate modifications mentioned in paragraphs describing the method of manufacture of Fig. 1 (mainly paragraph [0059]). These are device claims, which deal with structure. Species 1, Embodiment I, Fig. 1 (paragraphs [0043] through [0054]) does not include a plurality of semiconductor integrated circuit components and/or a plurality of passive components. Therefore, claims 7-15, 17, 18 and 20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DELACRUZ et al. (DELACRUZ) (US 2020/0075553 A1).
In regards to claim 1, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses a stacked semiconductor package (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A) comprising: a first substrate (items 232, 332, 432); a three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) stacked, in a first direction with respect to the first substrate (items 232, 332, 432); and a first connection member (items 238, 338, 438) for connecting the first substrate (items 232, 332, 432) to the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of components (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) each of which includes a semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and a passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) stacked in the first direction, a first major surface (top surfaces of items 232, 332, 432), which faces the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), of the first substrate (items 232, 332, 432) and a first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), which faces the first substrate (items 232, 332, 432), of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) are connected to each other with the first connection member (items 238, 338, 438) interposed therebetween while being separated from each other, a first major surface (top surface of items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), which faces the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), of the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and a first major surface (bottom surface of items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), which faces the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), of the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), each include a flat surface, and the flat surface of the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and the flat surface of the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) are bonded together while being in contact with each other.
In regards to claim 4, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of the semiconductor integrated circuit components (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), and the plurality of semiconductor integrated circuit components (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) are configured in order in the first direction or a direction orthogonal to the first direction.
In regards to claim 5, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of the passive components (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), and the plurality of passive components (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) are configured in order in the first direction or a direction orthogonal to the first direction.
In regards to claim 6, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses further comprising: a second substrate (items 210, 310, 410); and a second connection member (items 236, 336, 436), wherein the first substrate (items 232, 332, 432) is stacked in the first direction with respect to the second substrate (items 210, 310, 410), a second major surface (bottom surface of items 232, 332, 432), which faces the second substrate (items 210, 310, 410), of the first substrate (items 232, 332, 432), and a first major surface (top surface of items 210, 310, 410), which faces the first substrate (items 232, 332, 432), of the second substrate (items 210, 310, 410), are separated from each other and connected to each other with the second connection member (items 236, 336, 436) interposed therebetween, and a distance between the second major surface (bottom surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (top surface of items 210, 310, 410) of the second substrate (items 210, 310, 410) is larger than a distance between the first major surface (top surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over DELACRUZ et al. (DELACRUZ) (US 2020/0075553 A1).
In regards to claim 2, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses wherein an area of the flat surface of the semiconductor integrated circuit component is larger than half of an area of the first major surface of the semiconductor integrated circuit component, and an area of the flat surface of the passive component is larger than half of an area of the first major surface of the passive component.
It would have been obvious to modify the invention to include an area of the flat surface of the semiconductor integrated circuit component being larger than half of an area of the first major surface of the semiconductor integrated circuit component, and an area of the flat surface of the passive component being larger than half of an area of the first major surface of the passive component, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 19, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses further comprising: a second substrate (items 210, 310, 410); and a second connection member (items 236, 336, 436), wherein the first substrate (items 232, 332, 432) is stacked in the first direction with respect to the second substrate (items 210, 310, 410), a second major surface (bottom surface of items 232, 332, 432), which faces the second substrate (items 210, 310, 410), of the first substrate (items 232, 332, 432), and a first major surface (top surface of items 210, 310, 410), which faces the first substrate (items 232, 332, 432), of the second substrate (items 210, 310, 410), are separated from each other and connected to each other with the second connection member (items 236, 336, 436) interposed therebetween, and a distance between the second major surface (bottom surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (top surface of items 210, 310, 410) of the second substrate (items 210, 310, 410) is larger than a distance between the first major surface (top surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C).
Claim(s) 3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over DELACRUZ et al. (DELACRUZ) (US 2020/0075553 A1) in view of NIDLENOSHTHED et al. (NIDLENOSHTHED) (CN 103426909 A).
In regards to claims 3 and 16, DELACRUZ does not specifically disclose wherein the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component each include an inorganic substance.
NIDLENOSHTHED discloses “integrated electrical, optical or electromechanical circuit or passive device. a power semiconductor chip may contain inorganic and/or organic material is a semiconductor”, thus wherein the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component each include an inorganic substance.
It would have been obvious to modify the invention to include a flat surface of the semiconductor integrated circuit component and a flat surface of the passive component each including an inorganic substance, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rup et al. (CN 102738227 A) also discloses “integrated electrical, optical or electromechanical circuit or passive device. a power semiconductor chip may contain inorganic and/or organic material is a semiconductor”. Oseimetz (CN 102680749 A) discloses a semiconductor chip may comprise an inorganic and/or an organic material.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 March 28, 2026