DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4-6, 17-19 and 21 have been considered but are moot on grounds of new rejection. Claim 22 has been withdrawn due to the fact it is drawn to a non-elected invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over DELACRUZ et al. (DELACRUZ) (US 2020/0075553 A1) as evidenced by NIDLENOSHTHED et al. (NIDLENOSHTHED) (CN 103426909 A) in view of Haba et al. (Haba) (US 2020/0294908 A1).
In regards to claim 1, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses a stacked semiconductor package (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A) comprising: a first substrate (items 232, 332, 432); a three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) stacked, in a first direction with respect to the first substrate (items 232, 332, 432); and a first connection member (items 238, 338, 438) for connecting the first substrate (items 232, 332, 432) to the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of components (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) each of which includes a semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and a passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) stacked in the first direction, a first major surface (top surfaces of items 232, 332, 432), which faces the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), of the first substrate (items 232, 332, 432) and a first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C), which faces the first substrate (items 232, 332, 432), of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) are connected to each other with the first connection member (items 238, 338, 438) interposed therebetween while being separated from each other, a first major surface (top surface of items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), which faces the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), of the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and a first major surface (bottom surface of items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), which faces the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), of the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), each include a flat surface, and the flat surface of the semiconductor integrated circuit component (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) and the flat surface of the passive component (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) are bonded together while being in contact with each other.
DELACRUZ does not specifically disclose wherein an entirety of each of the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component is formed of at least one inorganic substance where the semiconductor integrated component and the flat surface of the passive component are bonded together.
As evidence by NIDLENOSHTHED (paragraph 17), “integrated electrical, optical or electromechanical circuit or passive device. a power semiconductor chip may contain inorganic and/or organic material is a semiconductor”, thus wherein the flat surface of the semiconductor integrated circuit component and the flat surface of the passive component each include an inorganic substance.
Haba (Figs. 1, 2, and associated text) discloses wherein an entirety of each of the flat surface (flat surface of 2, 8b) of the semiconductor integrated circuit component (items 2 or 37 plus 11 plus 8b) and the flat surface (flat surface of item 3, 8a) of the passive component (item 3) is formed of at least one inorganic substance (copper and silicon oxide, paragraph 60) where the semiconductor integrated component (item 2) and the flat surface (flat surface of item 3, 8a) of the passive component (item 3) are bonded together.
It would have been obvious to modify the invention to incorporate the teachings of NIDLENOSHTHED and/or Haba, “an entirety of each of the flat surface of the semiconductor integrated circuit component and a flat surface of the passive component formed of at least one inorganic substance”, the , since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 2, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) as modified by NIDLENOSHTHED and Haba (Figs. 1A, 1B and associated text) discloses wherein an area of the flat surface of the semiconductor integrated circuit component is larger than half of an area of the first major surface of the semiconductor integrated circuit component, and an area of the flat surface of the passive component is larger than half of an area of the first major surface of the passive component.
It would have been obvious to modify the invention to include an area of the flat surface of the semiconductor integrated circuit component being larger than half of an area of the first major surface of the semiconductor integrated circuit component, and an area of the flat surface of the passive component being larger than half of an area of the first major surface of the passive component, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claims 4 and 17, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) as modified by NIDLENOSHTHED and Haba (Figs. 1A, 1B, 11A-13C and associated text) discloses wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of the semiconductor integrated circuit components (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C), and the plurality of semiconductor integrated circuit components (items 214-B, 314 -A, 314-B plus 312-B, 414-A, 414-B or 414-C) are configured in order in the first direction or a direction orthogonal to the first direction.
In regards to claims 5 and 18, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) as modified by NIDLENOSHTHED and Haba (Figs. 1A, 1B, 11A-13C and associated text) discloses wherein the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) includes a plurality of the passive components (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C), and the plurality of passive components (items 212-B, 318-A, 318-B, 415-A, 415-B or 415-C) are configured in order in the first direction or a direction orthogonal to the first direction.
In regards to claim 6, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses further comprising: a second substrate (items 210, 310, 410); and a second connection member (items 236, 336, 436), wherein the first substrate (items 232, 332, 432) is stacked in the first direction with respect to the second substrate (items 210, 310, 410), a second major surface (bottom surface of items 232, 332, 432), which faces the second substrate (items 210, 310, 410), of the first substrate (items 232, 332, 432), and a first major surface (top surface of items 210, 310, 410), which faces the first substrate (items 232, 332, 432), of the second substrate (items 210, 310, 410), are separated from each other and connected to each other with the second connection member (items 236, 336, 436) interposed therebetween, and a distance between the second major surface (bottom surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (top surface of items 210, 310, 410) of the second substrate (items 210, 310, 410) is larger than a distance between the first major surface (top surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C).
In regards to claim 19, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) discloses further comprising: a second substrate (items 210, 310, 410); and a second connection member (items 236, 336, 436), wherein the first substrate (items 232, 332, 432) is stacked in the first direction with respect to the second substrate (items 210, 310, 410), a second major surface (bottom surface of items 232, 332, 432), which faces the second substrate (items 210, 310, 410), of the first substrate (items 232, 332, 432), and a first major surface (top surface of items 210, 310, 410), which faces the first substrate (items 232, 332, 432), of the second substrate (items 210, 310, 410), are separated from each other and connected to each other with the second connection member (items 236, 336, 436) interposed therebetween, and a distance between the second major surface (bottom surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (top surface of items 210, 310, 410) of the second substrate (items 210, 310, 410) is larger than a distance between the first major surface (top surface of items 232, 332, 432) of the first substrate (items 232, 332, 432) and the first major surface (bottom surface of items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C) of the three-dimensional device (items 214-B plus 212-B, 314 -A plus 318-A, 314-B plus 312-B plus 318-B, 414-A plus 415-A, 414-B plus 415-B or 414-C plus 415-C).
In regards to claim 21, DELACRUZ (Figs. 2B, 3A, 4A, 4B, 4C, 4D, 8A and associated text and items) as modified by NIDLENOSHTHED and Haba (Figs. 1A, 1B, 11A-13C and associated text) discloses wherein the bond of the flat surface (flat surface of 2, 8b, Haba) of the semiconductor integrated circuit component (items 2 or 37 plus 11 plus 8b, Haba) and the flat surface (flat surface of item 3, 8a, Haba) of the passive component (item 3, Haba) has a bond strength of 1N or more. Examiner notes that Haba disclose some of the same inorganic substances of the Applicant and would therefore share the same characteristics.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 15, 2026
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