Attorney Docket Number: T1516.10905US01
Filing Date: 5/24/2023
Inventors: Chen et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendment filed 1/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 1/02/2026, responding to the Office action mailed 10/01/2025, has been entered. Applicant amended claims 1, 5, 9-10, 16-20, cancelled claim 14 and added claim 21. The present Office action is made with all the suggested amendments being fully considered.
Amendment Status
Applicant’s amendments to the claims have overcome the claim objections and claim rejections under 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 10/01/2025. Accordingly, pending in this application are claims 1-13 and 15-21. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 20210375708 A1) in view of Feng (US 20240321749 A1) further in view of Morita (US 20200168563 A1).
Regarding claim 17, Kuo (see, e.g., rotated arrangement of fig. 15B) shows most aspects of the instant invention, including a package structure (e.g., package structure 104A + components 104A’) comprising:
a redistribution structure (e.g., front-side redistribution structure 444), wherein the redistribution structure (e.g., front-side redistribution structure 444) comprising:
a first conductive feature (e.g., metal pillars 562);
A first metal cap layer (e.g., first metal cap layer 564, see annotated fig. 1) lining a top surface (e.g., topmost surface (note fig. 15B should be flipped upside-down) of metal pillar 562) of the first conductive feature (e.g., metal pillars 562);
A dielectric layer (e.g., underfill material 666) covering the first metal cap layer (e.g., first metal cap layer 564, see annotated fig. 1);
A second conductive feature (e.g., through-via 72) over the dielectric layer (e.g., underfill material 666) and electrically coupled to the first metal cap layer (e.g., first metal cap layer 564, see annotated fig. 1);
A second metal cap layer (e.g., second metal cap layer 564, see annotated fig. 1);
A device comprising a third conductive feature (e.g., through-via 72 in annotated fig. 1 below) bonded (e.g., note the bonded conductive pillar 58 connecting the third conductive feature and the second metal cap layer) with the second metal cap layer (e.g., second metal cap layer 564, see annotated fig. 1);
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Annotated Fig. 1
Kuo (see, e.g., fig. 15A), however, fails to show the first conductive feature comprises nano-twinned copper, while it also fails to show the first metal cap layer lining a sidewall of the first conductive feature and a second metal cap layer lining a sidewall and a top surface of the second conductive feature.
Feng (see, e.g., fig. 1), in a similar device to Kuo, teaches a conductive feature within an RDL circuit comprising nano-twinned copper (see, e.g., paragraph 5 “Nanotwinned Cu is known to have high thermal stability, high electrical conductivity, and relatively lower CTE, which should be a good candidate for Cu RDL circuits. Recently, grain engineering approach has been focused on using (111) oriented nano twined Cu as the electrical circuit due to its high surface diffusivity and successfully eliminated bonding interface”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nano-twinned copper of Feng within the conductive feature of Kuo, in order to increase the electrical conductivity and stability within the redistribution structure of the device.
Kuo in view of Feng, however, fails to teach the first metal cap layer lining a sidewall of the first conductive feature and a second metal cap layer lining a sidewall and a top surface of the second conductive feature.
Morita (see, e.g., fig. 1J), in a similar device to Kuo in view of Feng, teaches a metal cap layer (e.g., cap layer 14) lines a sidewall of a first conductive feature (e.g., conductive layer 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal cap extension configuration of Morita within the metal cap layer along a sidewall of the conductive layer of Kuo in view of Feng, in order to increase the protective capping profile around a larger area of the first conductive feature within the device. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extended metal cap layer configuration of Morita around the second conductive feature of Kuo in view of Feng further in view of Morita (extending around the conductive pillar 58), in order to achieve the expected result of providing a protective profile around the second conductive feature.
Regarding claim 18, Kuo shows a connector (e.g., conductive connector 58) bonding (see, e.g., paragraph 171 “the packages 104A are bonded to the components 104A′ through a solder bonding or a direct metal to-metal (such as a copper-to-copper or tin-to-tin) bonding. In some embodiments, the packages 104A are bonded to the components 104A′ by a reflow process. During this reflow process, the conductive pillars 562 and the conductive connector 58 are in contact with the pads of the RDL structure 444 to electrically couple the packages 104A to the components 104A”) the third conductive feature (e.g., through-via 72, see annotated fig. 1 above) to the second metal cap layer (e.g., second metal cap layer 564, see annotated fig. 1 above).
Regarding claim 19, Kuo (see, e.g., fig. 15A) fails to show wherein the first metal cap layer comprises nano-twinned metal.
Feng (see, e.g., fig. 1) teaches a metallic layer comprising nano-twinned copper (see, e.g., paragraph 5 “Nanotwinned Cu is known to have high thermal stability, high electrical conductivity, and relatively lower CTE, which should be a good candidate for Cu RDL circuits. Recently, grain engineering approach has been focused on using (111) oriented nano twined Cu as the electrical circuit due to its high surface diffusivity and successfully eliminated bonding interface”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nano-twinned copper of Feng within the first metal cap layer of Kuo in view of Feng further in view of Morita, in order to increase the electrical conductivity and stability within the first metal cap layer of the device.
Regarding claim 20, Kuo (see, e.g., fig. 15B) shows wherein the first metal cap layer (e.g., metal cap layer 564) comprises silver, gold, tin, or palladium (see, e.g., paragraph 168 “…the metal cap layer 564 may include…gold, copper, silver, palladium…”).
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of Feng further in view of Morita and Miao (US 20170110416 A1).
Regarding claim 1, Kuo (see, e.g., fig. 15A to 15B) shows most aspects of the instant invention, including a method comprising:
Forming (see, e.g., paragraph 165 “A front-side redistribution structure 444 is formed over front-side surfaces of the IC dies 126 and 127…”) a redistribution structure (e.g., front-side redistribution structure 444), wherein the redistribution structure (e.g., front-side redistribution structure 444) comprises an interconnect structure (e.g., interconnect structure 132) and a first conductive feature (e.g., metal pillars 562) comprises a conductive layer (e.g., metal pillars 562) over the interconnect structure ;
Depositing a metal cap layer (e.g., metal cap layer 564 + paragraph 168 “Metal cap layer 564 are formed on the metal pillars 562”) over the first conductive feature (e.g., metal pillars 562); wherein the metal cap layer (e.g., metal cap layer 564) has a first portion extending along a top surface (e.g., topmost surface of metal pillar 562) of the conductive layer (e.g., top surface of metal pillars 562);
Bonding (see, e.g., paragraph 171 “Referring to FIG. 15B, the packages 104A are bonded to the components 104A′ through a solder bonding or a direct metal to-metal (such as a copper-to-copper or tin-to-tin) bonding. In some embodiments, the packages 104A are bonded to the components 104A′ by a reflow process. During this reflow process, the conductive pillars 562 and the conductive connector 58 are in contact with the pads of the RDL structure 444 to electrically couple the packages 104A to the components 104A′. After the bonding process, an intermetallic compound (IMC) (not shown) may form at the interface of the conductive pillars 562 and the metal cap layers 564, and the interface of the conductive pillars 58 and the metal cap layers 564.”) the first portion of the metal cap layer (e.g., metal cap layer 564) over the first conductive feature (e.g., metal pillars 562) of the redistribution structure (e.g., front-side redistribution structure 444) with a second conductive feature (e.g., through-via 72) of a device (components 104A’).
Kuo (see, e.g., fig. 15A), however, fails to show the metal cap layer has a second portion extending along a sidewall of the first conductive feature and the first conductive feature comprises an adhesive layer, a seed layer over the adhesive layer, and the conductive layer is over the seed layer, and the conductive layer comprising nano-twinned copper.
Feng (see, e.g., fig. 1), in a similar device to Kuo, teaches a conductive feature within an RDL circuit comprising nano-twinned copper (see, e.g., paragraph 5 “Nanotwinned Cu is known to have high thermal stability, high electrical conductivity, and relatively lower CTE, which should be a good candidate for Cu RDL circuits. Recently, grain engineering approach has been focused on using (111) oriented nano twined Cu as the electrical circuit due to its high surface diffusivity and successfully eliminated bonding interface”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nano-twinned copper of Feng within the conductive layer of Kuo, in order to increase the electrical conductivity and stability within the redistribution structure of the device.
Kuo in view of Feng, however, fails to teach the metal cap layer has a second portion extending along a sidewall of the first conductive feature, while it also fails to teach the first conductive feature comprises an adhesive layer and a seed layer over the adhesive layer.
Morita (see, e.g., fig. 1J), in a similar device to Kuo in view of Feng, teaches a conductive feature (e.g., structure comprising adhesion layer 4 + wiring growing layer 8a (see paragraph 33) + conductive layer 10) comprises an adhesive layer (e.g., adhesion layer 4), a seed layer (e.g., wiring growing layer 8a + paragraph 33), and a conductive layer (e.g., conductive layer 10) over the seed layer (e.g., wiring growing layer 8a + paragraph 33), and a metal cap layer (e.g., cap layer 14) has a second portion extending along a sidewall of the seed layer (e.g., wiring growing layer 8a + paragraph 33).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the adhesion layer and seed layer of Morita within the first conductive feature and under the conductive layer of Kuo in view of Feng, in order to provide an improved bonding profile between the first conductive feature and the rest of the device, in addition to increasing the uniform current path during the electroplating process respectively. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal cap extension configuration of Morita within the metal cap layer along a sidewall of the seed layer of Kuo in view of Feng further in view of Morita, in order to increase the protective capping profile around a larger area of the first conductive feature within the device.
Kuo in view of Feng further in view of Morita, however, fails to teach the metal cap layer extends along a sidewall of the adhesive layer.
Miao, in a similar device to Kuo in view of Feng further in view of Morita, teaches a metal cap layer (e.g., metal cap 770) extending along a sidewall of an adhesive layer (e.g., adhesive protective piece 130).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include extend the metal cap layer of Kuo in view of Feng further in view of Morita to adopt the sidewall-cover configuration between the metal cap layer and adhesive metal layer of Miao, in order to achieve the expected result of providing a protective structure of the adhesion layer within the first conductive feature.
Regarding claim 2, Kuo (see, e.g., fig. 15A) shows that depositing the metal cap layer (e.g., metal cap layer 564) over the first conductive feature (e.g., metal pillars 562) is formed by a plating process (see, e.g., paragraph 168 “…and may be formed by a plating process.”).
While Kuo fails to explicitly disclose this plating process is done without external current, an alternate embodiment (see, e.g., fig. 2A) shows an electroless plating methodology is a known plating process (see, e.g., paragraph 38 “The conductive material 117 may be formed by plating, such as…electroless plating…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the electroless plating process of the alternate embodiment to deposit the metal cap layer over the first conductive feature, as electroless plating was a known type of plating process, as disclosed by the alternate embodiment.
Regarding claim 3, Kuo (see, e.g., fig. 15A) shows that depositing the metal cap layer (e.g., metal cap layer 564) is formed by a plating process (see, e.g., paragraph 168 “…and may be formed by a plating process.”).
While Kuo fails to explicitly disclose this plating process comprises an electroless plating process or an immersion plating process, an alternate embodiment (see, e.g., fig. 2A) shows an electroless plating methodology is a known plating process (see, e.g., paragraph 38 “The conductive material 117 may be formed by plating, such as…electroless plating…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the electroless plating process of the alternate embodiment to deposit the metal cap layer over the first conductive feature, as electroless plating was a known type of plating process, as disclosed by the alternate embodiment.
Regarding claim 4, Kuo (see, e.g., fig. 15A) shows the metal cap layer (e.g., metal cap layer 564) comprises silver, gold, tin, or palladium (see, e.g., paragraph 168 “…the metal cap layer 564 may include…gold, copper, silver, palladium…”).
Regarding claim 5, Kuo (see, e.g., fig. 15A) shows wherein the interconnect structure (e.g., interconnect structure 132) has a portion uncovered by the first conductive feature (e.g., metal pillars 562), and depositing the metal cap layer (e.g., metal cap layer 564) over the first conductive feature (e.g., metal pillars 562) is performed such that portion of the interconnect structure (e.g., interconnect structure 132) uncovered by the first conductive feature (e.g., metal pillars 562) is free of a metal material (e.g., note that interconnect structure 132 is formed away from that of the metal cap layer 564) of the metal cap layer (e.g., metal cap layer 564).
Regarding claim 6, Kuo (see, e.g., fig. 15B) shows bonding the first portion of the metal cap layer (e.g., metal cap layer 564) over the first conductive feature (e.g., metal pillars 562) of the redistribution structure (e.g., front-side redistribution structure 444) with the second conductive feature (e.g., through-via 72) of the device (e.g., components 104A’) comprises:
forming a connector (e.g., conductive connector 58) over the first portion of the metal cap layer (e.g., metal cap layer 564);
attaching the connector (e.g., conductive connector 58) to the second conductive feature (e.g., through-via 72) of the device (e.g., components 104A’).
Regarding claim 7, Kuo (see, e.g., fig. 15A) fails to show depositing the metal cap layer is performed such that a part of the first portion of the metal cap layer comprises nano-twinned metal.
Feng (see, e.g., fig. 1), in a similar device to Kuo, teaches a metallic layer comprising nano-twinned copper (see, e.g., paragraph 5 “Nanotwinned Cu is known to have high thermal stability, high electrical conductivity, and relatively lower CTE, which should be a good candidate for Cu RDL circuits. Recently, grain engineering approach has been focused on using (111) oriented nano twined Cu as the electrical circuit due to its high surface diffusivity and successfully eliminated bonding interface”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nano-twinned copper of Feng within the first portion of the metal cap layer of Kuo, in order to increase the electrical conductivity and stability within the top surface of the metal cap layer of the device.
Regarding claim 8, Kuo (see, e.g., fig. 15A) fails to show depositing the metal cap layer is performed such that a part of the second portion of the metal cap layer comprises nano-twinned metal.
Feng (see, e.g., fig. 1) teaches a metallic layer comprising nano-twinned copper (see, e.g., paragraph 5 “Nanotwinned Cu is known to have high thermal stability, high electrical conductivity, and relatively lower CTE, which should be a good candidate for Cu RDL circuits. Recently, grain engineering approach has been focused on using (111) oriented nano twined Cu as the electrical circuit due to its high surface diffusivity and successfully eliminated bonding interface”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the nano-twinned copper of Feng within the second portion of the metal cap layer of Kuo in view of Feng further in view of Moria and Miao, in order to increase the electrical conductivity and stability within the vertical surface of the metal cap layer of the device.
Regarding claim 9, Morita (see, e.g., fig. 1J) teaches wherein the adhesive layer (e.g., adhesion layer 4a) is made of titanium (see, e.g., paragraph 30 “The adhesion layer 4a is formed from, for example, titanium or chromium…”) or titanium copper.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the titanium of Morita within the adhesive layer of Kuo in view of Feng further in view of Morita and Miao, as titanium was a well-known material to use as an adhesion layer within a conductive feature, as taught by Morita.
Allowable Subject Matter
Claims 10-13 and 15-16 are allowed.
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, Kuo (US 20210375708 A1) in view of Feng (US 20240321749 A1) further in view of Preisler (US 20240128209 A1) teaches most aspects of the method.
However, Kuo in view of Feng further in view of Preisler fails to teach wherein the metal cap layer is made of a metal material different from copper, and the metal cap layer also includes nano-twinned structure.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered
obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment
of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such
admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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