DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 30, 33 and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, taken alone or in combination, fails to disclose or render obvious a method comprising, among other things, wherein the electro-optic effect material layer is made of graphene or forming a package layer surrounding the electrical device and over the optical interposer, wherein a sidewall surface of the optical interposer extends beyond a sidewall surface of the package layer.
The closest relevant prior art of record, Yoshimura et al. (U.S. Patent # 6,611,635 B1), fails to teach or suggest such features.
Claim Objections
Claim 22 is objected to because of the following informalities: “third” should read “second”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17, 18, 20 – 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimura et al. (U.S. Patent # 6,611,635 B1).
In Re claim 17, ‘635 teaches a method for forming a package structure (figs. 36, 37-2, 37-3), comprising: forming an electrical device (351 as cited below as orientation is not defined) over a front-side surface of a substrate (302b); forming a first optical device (324a of 350 or 326) over a back-side surface of the substrate; forming an electro-optic effect material layer (3xx, col. 37, lines 27 – 38) below the first optical device; and forming a protective layer (bottom of inverted 320a, or 324a or bonding sheet 302’ as seen in figs. 36 and not labeled in 37-2) below the electro-optic effect material layer.
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In Re claim 18, ‘635 teaches removing a portion of the substrate; and forming a through-substrate via (TSV) structure through the substrate (col. 14, lines 47 – 60 col. 15, lines 18 – 22).
In Re claim 20, ‘635 teaches an optical interposer as claimed (324a of 320a).
In Re claim 21, ‘635 teaches TSVs (333, col. 37 – 40) through a substrate (320a).
In Re claim 22, ‘635 teaches optical device (324a).
In Re claim 23, ‘635 teaches an interconnect structure as claimed (324a).
In Re claim 24, ‘635 teaches forming a package layer (350) surrounding the first optical device (324a); and removing a portion of the package layer (where via 333 resides).
In Re claim 25, ‘635 teaches forming an optical interposer (320a) below the first optical device, wherein a width of the optical interposer is greater than a width of the protective layer (302’, as seen in fig. 36, 302’ is not as wide as the interposer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 19, 26 – 29, 31, 32, 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura et al. (U.S. Patent # 6,611,635 B1).
In Re claim 26, ‘635 teaches a method for forming a package structure (figs. 36, 37-2, 37-3, inverted), comprising: forming an electrical device (351) over a front-side surface of a substrate (320b); forming a contact plug (333) below the electrical device; forming a first optical device (324a in 350) over a back-side surface of the substrate; forming an electro-optic effect material layer (3xx, figs. 37-2, 37-3, col. 37, lines 27 – 38) below the first optical device; and forming an interconnect structure (302’ or 320a) below the electro-optic effect material layer.
‘635 is silent to wherein the electrical device comprises a plurality of nanostructures, and a gate structure formed on the nanostructures.
However, it is well known in the art that drivers and/or amplifiers such as 351 are made up of electrical traces, which are nanostructures as they can be measured in nanometers, which connect to transistors having a source, drain and a gate such as field effect transistors, which allow for low power and fast switching operation of the drivers and/or amplifiers.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrical device of ‘635 to have transistors such as FETS using a source, drain and gate, each connected to a nanostructure for electrical operation, so as to allow for lower power consumption and fast switching operation, thereby allowing for high speed and low power operation as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
In Re claim 27, ‘635 teaches forming a first bonding layer (320a or pad 330) below the interconnect structure.
In Re claim 28, ‘635 teaches bonding the first bonding layer to an optical interposer (324a in 320a), but is silent to forming a package layer surrounding the electrical device and over the optical interposer.
However, it is well known in the art to house optoelectronic packages in a housing to protect from extreme environmental conditions.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of ‘635 to add a housing, a package layer, to surround the package so as to protect the package from extreme environmental conditions as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
In Re claim 29, ‘635 teaches wherein the optical interposer comprises a plurality of TSV structures formed through a substrate (col. 43, line 37 – 40).
In Re claim 31, ‘635 teaches a method for forming a package structure (figs. 36, 37-2, 37-3), comprising: forming an electrical device (top 351 in inverted figure below as orientation of the package is not defined) over a front-side surface of a substrate (302b); forming a plurality of TSV structures (333) below the electrical device; forming a first optical device (324a) over a back-side surface of the substrate; forming an electro-optic effect material layer (3xx, col. 37, lines 27 – 38) below the first optical device; forming a first bonding layer (302’) below the electro-optic effect material layer; and bonding the first bonding layer to an optical interposer (324a in 320a).
‘635 is expressly silent to wherein the electrical device comprises a gate structure and an S/D structure.
It is well known in the art that driver and/or amplifiers such as 351 are constructed of transistors having a source, drain and a gate such as field effect transistors, which allow for low power and fast switching operation.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrical device of ‘635 to have transistors such as FETS using a source, drain and gate so as to allow for lower power consumption and fast switching operation, thereby allowing for high speed and low power operation.
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In Re claims 19 and 32, ‘635 teaches the package and vertically coupling light via surface 344, and a bonding layer (302’), but is silent to a grating coupler as claimed in the current embodiment. Col. 29, lines 1 – 5 of ‘635 teaches using a grating in place of a vertical coupler.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make a grating as claimed as the vertical coupler of 344 of layer 320a as gratings allow for reflection of desired wavelengths, thus allowing for more control over the wavelengths transmitted as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
In Re claim 35, ‘635 teaches an interconnect structure as claimed (320b contains modulator 3xx, as seen in fig. 37-2 is located at 302’ under optical device as cited).
In Re claim 36, ‘635 teaches a protective layer as claimed (layer 320a surrounding 324a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAD H SMITH/Primary Examiner, Art Unit 2874
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