Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 9, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharma (US 20220187536 A1).
Regarding claim 1, Sharma discloses, in FIG. 12D, an integrated circuit package comprising a “package substrate” 202; a “die” (“die 204-1 may include any of the IC structures disclosed herein” [0147], this is a first integrated circuit die) 204-1 electrically coupled to the package substrate (note “interconnects” 210) ; “die” (second IC die) 204-2 electrically coupled to the first IC die (“die 204-2 may include any other of the IC structures disclosed herein so that the IC structure of the die 204-1 is bonded to the IC structure of the die 204-2 using hybrid bonding for integrating photonic and electronic components as described herein” [0147]), wherein the second IC die is above or below the first IC die (see FIG. 12D); and a “bonding material” (“the bonding material 130 may be applied to the one or both faces of the IC structures 110 and 120 . . . possibly while applying a suitable pressure and heating up the assembly to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 200 degrees Celsius) for a duration of time” [0063], the examiner notes that this therefore constitutes a thermoset adhesive) that partially fills an area between the first IC die and the second IC die (see FIG. 12d).
Regarding claim 2, Sharma further discloses, in [0059] “. . . one or both of the IC structures 110, 120 may include, or be a part of, one or more of a central processing unit, a memory device, e.g., a high-bandwidth memory device, a logic circuit, input/output circuitry . . . Furthermore, some embodiments, one or both of the IC structures 110, 120 may include one or more of a PIC . . .” and, as explained above, Sharma discloses “In some embodiments, the die 204-1 may include any of the IC structures disclosed herein and the die 204-2 may include any other of the IC structures disclosed herein so that the IC structure of the die 204-1 is bonded to the IC structure of the die 204-2 using hybrid bonding for integrating photonic and electronic components as described herein” [0147]. The examiner notes that the first IC is therefore an EIC and the second die is a PIC, as disclosed by Sharma in FIG. 12D.
Regarding claim 4, Sharma further discloses, in FIG. 12D, that the area between the first IC die and the second IC die comprises: one or more first areas between the EIC and the PIC, wherein the one or more first areas are filled with the thermoset adhesive; and one or more second areas between the EIC and the PIC, wherein the one or more second areas are not filled with the thermoset adhesive.
Regarding claim 9, Sharma further discloses, in FIG. 12D, a third IC die 204-3, coupled to the substrate (note “interconnects” 230) wherein “die 204-3 may include any of the IC structures disclosed herein” [0167]. The examiner notes that the above cited [0059] lists “high-bandwidth memory device, a logic circuit, [or] input/output circuitry . . .“ as devices the third IC die can be.
Regarding claim 11, Sharma further discloses, in FIG. 12D, that the thermoset adhesive 130 has an irregular geometry (note “after-bonding vias’” 140 which break up the shape of the thermoset adhesive, rendering its geometry irregular).
Claim(s) 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by T. Lin (US 20230282607 A1).
Regarding claim 16, T. Lin discloses in [0041]: ”Turning to FIG. 6, one or more discrete thermoset regions 126 of non-conductive adhesive are applied to the upper surface 112 or the bottom surface 116 of the die(s) (block 602)” (receiving a first semiconductor device, dispensing a thermoset adhesive on the first semiconductor device, wherein the thermoset adhesive is dispensed one or more patterns on a surface of the first semiconductor device); “. . . The die 102 can be aligned and attached (block 606)” (and after dispensing the thermoset adhesive on the first semiconductor device, attaching a second semiconductor device to the surface of the first semiconductor device). The examiner notes that FIG. 6 shows that the attaching step comes after the dispensing of thermoset adhesive on the first semiconductor device.
Regarding claim 17, T. Lin further discloses, in FIG. 4, “thermoset regions” 126 which are patterned in dots.
Regarding claim 18, T. Lin, in FIG. 6, further teaches that a “thermal compression bonding process” is done as a means attaching the second semiconductor device to the surface of the first semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5-6, and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 20220187536 A1) in view of Lin (US 20220392873 A1).
Regarding claim 3, Sharma teaches the limitations of claim 1, as explained above. Sharma does not explicitly teach that the EIC is to control the PIC.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Sharma such that the EIC is to control the PIC, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that the PIC is efficiently operated by using specialized hardware (an ASIC, which is an EIC) to control it; utilization of an ASIC to control another circuit is a known technique in the art which one having ordinary skill in the art would deploy with a reasonable expectation of success. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 5, Sharma teaches the limitations of claim 4, as explained above, Sharma further teaches, in FIG. 12D, that the EIC and the PIC are electrically coupled via a plurality of conductive contacts (see “after bonding vias 140), wherein the plurality of conductive contacts are located in at least one of the one or more first areas filled with the thermoset adhesive.
Regarding claim 6, as explained above, Sharma teaches the limitations of claim 4 as explained above, Sharma further teaches “A photonic integrated circuit (photonic IC (PIC)) is a device that integrates photonic functions for information signals imposed on electromagnetic waves, e.g., electromagnetic waves of optical wavelengths” [0003]. Furthermore, “For example, various embodiments described with reference to the after-bonding via 140 as shown in FIGS. 5-11 are applicable to embodiments where the after-bonding via 140 is replaced with the after-bonding waveguide 170 to enable optical coupling.” Also, FIG. 12A shows “fiber-optic cable” 270 which is located in a second area not filled with thermoset adhesive.
Lin further teaches, in [0016] “The PIC 108 may include germanium (Ge) photodiodes or photosensors to detect optical signals, couplers to receive or emit optical signals, waveguides, laser sources, and modulators.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the PIC taught by Sharma such that the “electromagnetic waves” for use by the PIC are lasers, as taught by Lin, furthermore it would have been obvious to emit these through the fiber-optic cables taught by Sharma, as this is the common use of fiber-optic cables. One having ordinary skill in the art is motivated to utilize lasers through optical cables because it amounts to the use of a known technique for its known purpose. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 12, Sharma teaches, in FIG. 12C, an electronic device comprising a “circuit board 218; and an integrated circuit package coupled to the circuit board (see package substrate 202, chips 204-1, 204-2), wherein the integrated circuit package comprises: a photonic integrated circuit (PIC) to send or receive optical signals and electronic integrated circuit (“a die 204-1, and a die 204-2 . . . In some embodiments, the die 204-1 may include any of the IC structures disclosed herein and the die 204-2 may include any other of the IC structures disclosed herein so that the IC structure of the die 204-1 is bonded to the IC structure of the die 204-2 using hybrid bonding for integrating photonic and electronic components as described herein” [0147], see above quotation of [0059] for PIC and EIC chip options referred to in “any other of the IC structures disclosed herein”), wherein the EIC is above or below the PIC, and wherein the EIC is electrically coupled to the PIC (see “after-bonding via 140); and a thermoset adhesive 130 (see above for discussion of thermoset adhesive 130) that partially fills an area between the EIC and the PIC (see FIG. 12C).
Sharma does not explicitly disclose that the EIC is to control the PIC.
Lin teaches an “HPC IC” (EIC) and a PIC in which “Each of the HPC IC 102 may serve as a switch to control optical engines 104 that each include an EIC 106 and a PIC 108” [0028].
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Sharma such that the EIC is to control the PIC, as taught by Lin. One having ordinary skill in the art is motivated to do so in order to, for example, ensure that the PIC is efficiently operated by using specialized hardware (an ASIC, which is an EIC) to control it; utilization of an ASIC to control another circuit is a known technique in the art which one having ordinary skill in the art would deploy with a reasonable expectation of success. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 13, Sharma further teaches, in FIG. 12A, that an area between the EIC and PIC comprises a first area filled with the thermoset adhesive, wherein the EIC and PIC are electrically coupled via conductive contacts located in the first area (see “after-bonding vias” 140); and a second area that is not filled with the thermoset adhesive, which houses “fiber optic cable” 270.
Sharma does not explicitly teach that the PIC is to emit laser beams through the second area.
Lin further teaches, in [0016] “The PIC 108 may include germanium (Ge) photodiodes or photosensors to detect optical signals, couplers to receive or emit optical signals, waveguides, laser sources, and modulators.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the PIC taught by Sharma such that the “electromagnetic waves” for use by the PIC are lasers, as taught by Lin, furthermore it would have been obvious to emit these through the fiber-optic cables in the second area taught by Sharma, as this is the common use of fiber-optic cables. One having ordinary skill in the art is motivated to utilize lasers through optical cables because it amounts to the use of a known technique for its known purpose. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 14, Regarding claim 9, Sharma further discloses, in FIG. 12D, a third IC die 204-3, coupled to the substrate (note “interconnects” 230) wherein “die 204-3 may include any of the IC structures disclosed herein” [0167]. The examiner notes that the above cited [0059] lists “high-bandwidth memory device, a logic circuit, [or] input/output circuitry . . .“ as devices the third IC die can be. The examiner also notes that Sharma teaches “the rest of the descriptions provided with respect to FIG. 12A-12C are applicable to, and may be combined with, the embodiment of FIG. 12D (and vice versa) . . .”
Regarding claim 15, Sharma further teaches, in [0208] “ FIG. 16 is a block diagram of an example computing device 1800 that may include one or more components with one or more microelectronic assemblies 100 fabricated using hybrid manufacturing for integrating photonic and electronic components in accordance with any of the embodiments disclosed herein.” [0216] teaches “The computing device 1800 may include a display device 1806 . . .” [0222] states “The computing device 1800 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, . . . a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, . . . an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.”
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 20220187536 A1) in view of Lin (US 20220392873 A1) in further view of Tabuchi (DE 4402422 A1).
Regarding claims 7 and 8, Sharma teaches the limitations of claim 4, as explained above, Sharma further teaches, in FIG. 12A, a “fiber optic cable” (optical fibers) 270 in the second area not filled with thermoset adhesive.
Sharma does not explicitly teach grooves to optically couple the PIC with the optical fibers.
Tabuchi teaches, in Abstract: “A method for the production of an integrated optical semiconductor arrangement comprises the following steps: formation of a groove for positioning an optical fibre [sic] on the surface of a substrate, levelling the surface of the substrate having the groove, positioning an optical component on the levelled surface, renewed clearing of the groove and assembling and positioning an optical fibre [sic] in the cleared groove.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Sharma such that the PIC comprises one or more grooves to optically couple the PIC with one or more optical fibers, as taught by Tabuchi. One having ordinary skill in the art is motivated to do so because in doing so “Various problems which arise from the presence of a groove for positioning an optical fibre [sic] on the surface of a substrate, and occur during the formation of an optical component or during bonding of a chip, can be solved. The production methods can be simplified and integrated chips can be bonded with high precision” (abstract).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 20220187536 A1) in view of Kodama (US 20140247584 A1).
Regarding claim 10, Sharma teaches the limitations of claim 1 (as explained above).
Sharma does not teach that the thermoset adhesive comprises an acrylic polymer and a silica filler.
Kodama teaches, in [0061] “Examples of the epoxy resin, acrylic resin and silicone resin include light curing (ultraviolet curing) adhesive, thermoset adhesive, two-part adhesive and the like. As a material of the joint member 24, it is preferable to use an adhesive with inorganic fillers (e.g., made of silica . . .” The examiner notes that “acrylic resin” refers to acrylic polymer.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the thermoset adhesive taught by Sharma such that it comprises an acrylic polymer and silica filler, as taught by Kodama. One having ordinary skill in the art is motivated to do so because, for example, “In a case where the joint member 24 is formed of the adhesive with inorganic fillers, it is possible to further suppress moisture permeation.” In addition, Acrylic polymer is one of several straightforward materials that one having ordinary skill in the art could utilize with a reasonable expectation of success as an adhesive. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over T. Lin (US 20230282607 A1) in further view of Sharma (US 20220187536 A1).
Regarding claim 19, as explained above, T. Lin teaches the limitations of claim 16. T. Lin does not explicitly teach that the first die is an EIC and that the second die is a PIC.
Sharma, as explained above, teaches a first die that is an EIC and a second die that is a PIC.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by T. Lin such that the first semiconductor device comprises an electronic integrated circuit (EIC); and the second semiconductor device comprises a photonic integrated circuit (PIC), as taught by Sharma. One having ordinary skill in the art is motivated to do because, for example, “Technological advances today enable implementing portions of some photonic components at the IC (or chip) level, which provides advantages for use of optical communications in computer systems. . . PICs find application in fiber-optic communication, medical, security, sensing, and photonic computing systems” (Sharma [0003]).
Regarding claim 20, as explained above, T. Lin further teaches, in [0003] “Semiconductor dies of a die stack, particularly thin dies, can warp during the mass reflow process, which may result in failure of the device. Different areas of the wafer from which the dies are selected, such as inner, middle, and outer locations with reference to the center of the wafer, can warp different amounts when exposed to heat.” The examiner notes that this denotes the existence of a “wafer” (substrate) in the die. One of ordinary skill in the art also appreciates that “die” refers to “integrated circuit die” unless indicated otherwise (for example, a dummy die). Also note that, in Abstract, Sharma states “. . . first and second dies that each have a plurality of conductive interconnect elements on upper surfaces. A portion of the interconnect elements are connected to through-silicon vias . . . ” The examiner notes that electrical interconnects elements and through-silicon vias further indicate the IC nature of the dies, as they require electrical connections.
It would have been obvious to one having ordinary skill in the art at the effective filing date to construct the device taught by T. Lin such that the second semiconductor device comprises an integrated circuit die. One having ordinary skill in the art is motivated to do so in order to gain the utility of an IC die (lending functionality to one of the many applications listed by Sharma in [0208] and [0222] above, for example).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Weng (US 20210223489 A1) – IC package comprising photonic chip(s) and EIC chips, as well as interconnects therebetween and an “optical coupler” 70 on the PIC.
Karhade (US 20220415770 A1) – “An electronic integrated circuit (EIC) 118 is physically and electrically coupled with the substrate 102 and the PIC 108” [0023].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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