CTNF 18/323,600 CTNF 90717 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyawaki(USPGPUB DOCUMENT: 2021/0074612, hereinafter Miyawaki) in view of Kiyonaga (USPGPUB DOCUMENT: 2020/0343155, hereinafter Kiyonaga) . Re claim 1 Miyawaki discloses in fig 9 a semiconductor device comprising: a semiconductor element(5); a first heat dissipation substrate(23/24) having the semiconductor element(5) mounted thereon; a heat dissipation block(15) Miyawaki does not discloses a semiconductor device comprising: a semiconductor element(5) having an electrode; a heat dissipation block(15) disposed to be opposed to the electrode; a second heat dissipation substrate disposed on a side opposite to the electrode as viewed from the heat dissipation block(15); and a bonding material covering a side surface of the heat dissipation block(15) and in contact with the electrode of the semiconductor element(5) and the second heat dissipation substrate. Kiyonaga discloses a semiconductor device comprising: a semiconductor element(10 of Kiyonaga) having an electrode(10b); a second heat dissipation substrate(51/50 of Kiyonaga) disposed on a side opposite to the electrode(10b of Kiyonaga); and a bonding material (20 of Kiyonaga) in contact(examiner interprets contact as electrical contact) with the electrode(10b of Kiyonaga) of the semiconductor element(10 of Kiyonaga) and the second heat dissipation substrate(51/50 of Kiyonaga). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Koyonaga to the teachings of Miyawaki in order to have improved heat dissipation in order to achieve miniaturization and higher output [0002, Kiyonaga]. In doing so, a heat dissipation block(15) disposed to be opposed to the electrode(10b of Kiyonaga); a second heat dissipation substrate(51/50 of Kiyonaga) disposed on a side opposite to the electrode(10b of Kiyonaga) as viewed from the heat dissipation block(15); and a bonding material (20 of Kiyonaga) covering a side surface of the heat dissipation block(15) and in contact(examiner interprets contact as electrical contact) with the electrode(10b of Kiyonaga) of the semiconductor element(10 of Kiyonaga) and the second heat dissipation substrate(51/50 of Kiyonaga). Re claim 2 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the semiconductor device includes a terminal[0024] having a first through hole(10), the terminal[0024] has a first terminal[0024] main surface facing the electrode(10b of Kiyonaga) of the semiconductor element(5),and a second terminal[0024] main surface opposite to the first terminal[0024] main surface, the first through hole(10) is formed to extend from the first terminal[0024] main surface and reach the second terminal[0024] main surface,the terminal[0024] is disposed between the electrode(10b of Kiyonaga) of the semiconductor element(5) and the second heat dissipation substrate(51/50 of Kiyonaga) such that the heat dissipation block(15) is disposed inside of the first through hole(10), andthe bonding material (20 of Kiyonaga) is in contact with the terminal[0024]. Re claim 3 Miyawaki and Koyonaga disclose the semiconductor device according to claim 2, wherein the bonding material (20 of Kiyonaga) extends from inside of the first through hole(10) onto the first terminal[0024] main surface and onto the second terminal[0024] main surface. Re claim 4 Miyawaki and Koyonaga disclose the semiconductor device according to claim 2, wherein the first through hole(10)has a recess formed in an inner peripheral surface of the first through hole(10). Re claim 5 Miyawaki and Koyonaga disclose the semiconductor device according to claim 2, wherein the first through hole(10) has a first region in which an area in a radial direction of the first through hole(10) is smallest, anda first opening area of the first through hole(10) on the first terminal[0024] main surface and a second opening area of the first through hole(10) on the second terminal[0024] main surface are larger than the area in the first region. Re claim 6 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the heat dissipation block(15) has a first heat dissipation block(15) main surface facing the electrode(10b of Kiyonaga) of the semiconductor element(5), anda second heat dissipation block(15) main surface opposite to the first heat dissipation block(15) main surface, anda first surface area of the first heat dissipation block(15) main surface is larger than a second surface area of the second heat dissipation block(15) main surface. Re claim 7 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the heat dissipation block(15) has a first heat dissipation block(15) main surface facing the electrode(10b of Kiyonaga) of the semiconductor element(5), anda second heat dissipation block(15) main surface opposite to the first heat dissipation block(15) main surface, andthe heat dissipation block(15) further has a second through hole(10) formed to extend from the first heat dissipation block(15) main surface and reach the second heat dissipation block(15) main surface. Re claim 8 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein a material forming the bonding material (20 of Kiyonaga) includes any one selected from the group consisting of solder, sinteredmaterial, and adhesive. Re claim 9 Miyawaki and Koyonaga disclose the semiconductor device according to claim 2, wherein any one selected from the group consisting of the electrode(10b of Kiyonaga), the terminal[0024], the second heat dissipation substrate(51/50 of Kiyonaga), and the heat dissipation block(15) includes a plating layer formed in a region in contact with the bonding material (20 of Kiyonaga). Re claim 10 Miyawaki and Koyonaga disclose the semiconductor device according to claim 9, wherein the plating layer includes at least one selected from the group consisting of nickel, silver, gold, and tin as a main component. Re claim 11 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the first heat dissipation substrate(23/24) and the second heat dissipation substrate(51/50 of Kiyonaga) include aluminum or copper as a main component. Re claim 12 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the first heat dissipation substrate(23/24) and the second heat dissipation substrate(51/50 of Kiyonaga) each have an insulating heat dissipation sheet connected to a surface opposite to surfaces facing each other, and the insulating heat dissipation sheet includes an insulating layer and a metal layer laminated on the insulating layer. Re claim 13 Miyawaki and Koyonaga disclose the semiconductor device according to claim 12, further comprising a cooler connected to the first heat dissipation substrate(23/24) or the second heat dissipation substrate(51/50 of Kiyonaga) with the insulating heat dissipation sheet interposed. Re claim 14 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, further comprising a cooler connected to the first heat dissipation substrate(23/24) or the second heat dissipation substrate(51/50 of Kiyonaga). Re claim 15 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, further comprising a sealing resin[0029] covering the semiconductor element(5), the first heat dissipation substrate(23/24), and the second heat dissipation substrate(51/50 of Kiyonaga). Re claim 16 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the semiconductor element(5) is an insulated gate bipolar transistor. Re claim 17 Miyawaki and Koyonaga disclose the semiconductor device according to claim 1, wherein the semiconductor element(5) includes a wide-bandgap semiconductor. Re claim 18 Miyawaki and Koyonaga disclose a power conversion device comprising:a main conversion circuit(3) having the semiconductor device according to claim 1, the main conversion circuit(3) converting input power and outputting the converted power;a drive circuit(3) to output a drive signal for driving the semiconductor device to the semiconductor device; anda control circuit(3) to output a control signal for controlling the drive circuit(3) to the drive circuit(3) . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyawaki(USPGPUB DOCUMENT: 2021/0074612, hereinafter Miyawaki) in view of Kiyonaga (USPGPUB DOCUMENT: 2020/0343155, hereinafter Kiyonaga) and Ide (USPGPUB DOCUMENT: 2013/0299962, hereinafter Ide) . Re claim 20 Miyawaki discloses in fig 9 a semiconductor device comprising: a semiconductor element(5); a first heat dissipation substrate(23/24) having the semiconductor element(5) mounted thereon; a heat dissipation block(15); Miyawaki does not discloses a semiconductor device comprising: a semiconductor element(5) having an electrode; a heat dissipation block(15) disposed to be opposed to the electrode; a second heat dissipation substrate disposed on a side opposite to the electrode as viewed from the heat dissipation block(15); and a bonding material entirely covering a side surface of the heat dissipation block(15) and in contact with the electrode of the semiconductor element(5) and the second heat dissipation substrate. Kiyonaga discloses a semiconductor device comprising: a semiconductor element(10 of Kiyonaga)having an electrode(10b of Kiyonaga); a heat dissipation block(15) disposed to be opposed to the electrode(10b of Kiyonaga); a second heat dissipation substrate(51/50 of Kiyonaga) disposed on a side opposite to the electrode as viewed from the heat dissipation block(15); and a bonding material(20 of Kiyonaga) in contact with the electrode of the semiconductor element(5) and the second heat dissipation substrate. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Koyonaga to the teachings of Miyawaki in order to have improved heat dissipation in order to achieve miniaturization and higher output [0002, Kiyonaga]. In doing so, a semiconductor element(10 of Kiyonaga)having an electrode(10b of Kiyonaga); a heat dissipation block(15) disposed to be opposed to the electrode(10b of Kiyonaga); a second heat dissipation substrate(51/50 of Kiyonaga) disposed on a side opposite to the electrode as viewed from the heat dissipation block(15); and a bonding material(20 of Kiyonaga) in contact with the electrode of the semiconductor element(5) and the second heat dissipation substrate. Miyawaki does not discloses a bonding material entirely covering a side surface of the heat dissipation block(15) Ide discloses in Fig 4C, rotated 90 degrees, a bonding material(68a/56a/66a of Ide) entirely covering a side surface of the heat dissipation block(70a) It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Ide to the teachings of Miyawaki in order to have improved incorporation of a semiconductor element excellent in heat-release properties [0005, Ide] . Response to Arguments 07-38 AIA Applicant’s arguments with respect to claim 1-18 & 20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812 Application/Control Number: 18/323,600 Page 2 Art Unit: 2812 Application/Control Number: 18/323,600 Page 3 Art Unit: 2812 Application/Control Number: 18/323,600 Page 4 Art Unit: 2812 Application/Control Number: 18/323,600 Page 5 Art Unit: 2812 Application/Control Number: 18/323,600 Page 6 Art Unit: 2812 Application/Control Number: 18/323,600 Page 7 Art Unit: 2812 Application/Control Number: 18/323,600 Page 8 Art Unit: 2812 Application/Control Number: 18/323,600 Page 9 Art Unit: 2812
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