Prosecution Insights
Last updated: April 19, 2026
Application No. 18/323,925

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102
Filed
May 25, 2023
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
700 granted / 829 resolved
+16.4% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
851
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
32.8%
-7.2% vs TC avg
§102
55.7%
+15.7% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 829 resolved cases

Office Action

§102
DETAILED ACTION Election/Restrictions Applicant’s election of claims 1-13 in the reply filed on 2/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuruoka et al. (Tsuruoka, US 2010/0295187 A1). Regarding claim 1, Tsuruoka shows a semiconductor module (FIG. 1) comprising: a first semiconductor chip (chip 8 in FIG. 1) including a first main electrode (conductor 5); a first connection conductor (conductor 6) electrically connected to the first main electrode (conductor 5); a housing portion (housing 10) surrounding the first semiconductor chip (chip 8) and at least a part of the first connection conductor; a first sealing (resin 17a) material filled in a space surrounded by the housing portion (housing 10); and a connection unit (connection conductor 14) fixed to the housing portion (housing 10), wherein a first conductive portion is exposed ( interface between 11 and 14 in FIG. 1) from a surface of the first sealing material (resing17a), the first conductive portion being a part of the first connection conductor ( connection conductor 14), and the connection unit includes: a first terminal (terminal 11) joined to the first conductive portion of the first connection conductor; and a support that is configured separately from the housing portion and supports the first terminal (see FIG. 1 and related text). Regarding claim 2, Tsuruoka shows a semiconductor module (FIG. 1) comprising, wherein a recess ( resin portion of 17b) is formed in the housing portion (housing 10), the support is accommodated in the recess, and a surface of the first sealing material (resin 17a) is at a position lower than a bottom surface of the recess (see FIG. 1). Regarding claim 4, Tsuruoka shows a semiconductor module (FIG. 1) further comprising a second sealing material (resin 17b) filled in a space surrounded by the housing (housing 10) portion and the support (see FIG. 1). Regarding claim 5, Tsuruoka shows a semiconductor module (FIG. 1) further comprising a protrusion ( see portion terminal 11) that protrudes from an inner wall surface of the support and is in contact with a bottom surface of the first terminal (see FIG. 1). Allowable Subject Matter Claims 3, 6-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 25, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
Patent 12604779
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2y 5m to grant Granted Apr 14, 2026
Patent 12599050
MULTI-LEVEL DIE COUPLED WITH A SUBSTRATE
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Patent 12593729
POWER MODULE HAVING AT LEAST THREE POWER UNITS
2y 5m to grant Granted Mar 31, 2026
Patent 12593697
INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 829 resolved cases by this examiner. Grant probability derived from career allow rate.

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