DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 12/01/2025.
Claims 1-19 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, claims 1-9, is acknowledged.
Claims 10-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 10/16/2024, 10/31/2024, and 02/27/2025. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Oath/Declaration
3. A properly executed inventor's oath or declaration has not been received for all inventors. An inventor's oath or declaration in compliance with 37 CFR 1.63 or 1.64 executed by or with respect to each inventor must be submitted no later than the date on which the issue fee is paid in response to a notice requiring such fee. See 37 CFR 1.53(f).
Foreign Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d); however, the foreign priority document has NOT been placed of record in the file. To properly claim for foreign priority, the PCT/CN2020/132301 must be placed of record in the file.
Specification
5. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objection
6. The claim is objected to for the following reason:
In claim 5, and claim 6, the limitations “the second sub-film layer” lacks an antecedent basis and indefinite. Correction is required.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-9 are rejected under 35 U.S.C. 102(a)(b) as being anticipated by Huang et al. (US 2020/0176389)
Regarding claim 1, Huang discloses a semiconductor device, comprising:
a substrate 510 (see fig. 5);
a first dielectric layer 530 & 550 having a first area (see Annotated Drawing below) and a second area disposed outside of the first area, a first thickness (thickness of layers 530 &550) of the first dielectric layer in the first area being greater than a second thickness (thickness of layers 530 &553; see also figs. 12C, 12D, fig. 13E, and para. 0053) of the first dielectric layer in the second area;
a gate 560, located on the substrate 510 in the first area, the gate comprising:
a first gate structure (portion of gate electrode 560 laterally surrounded by layers 530 & 553) penetrating the first area of the first dielectric layer in a direction perpendicular to a surface of the substrate; and
a second gate structure (portion of gate electrode 560 formed above layer 553) contacting the first gate structure, wherein the second gate structure covers the first gate structure and covers a part of the first dielectric layer 530 & 550;
a second dielectric layer 570 covering the first gate 560 and the first dielectric layer 530 &550; and
a field plate 580 having a part disposed on the second dielectric layer and that is disposed in both the first area and the second area.
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Regarding claim 2, Huang discloses the semiconductor device according to claim 1, further comprising:
a source 540, located in the substrate 510 (see para. 0025); and
a drain 545, located in the substrate, wherein the gate 560 is disposed between the source and the drain;
wherein the part of the field plate 580 disposed on the second dielectric layer 530 & 553 extends from the first area to the second area in a direction of the drain, and another part of the field plate is located in the second area and is electrically connected to the source (para. 0037).
Regarding claim 3, Huang discloses the semiconductor device according to claim 1, wherein the first dielectric layer 530 & 550 comprises:
a first layer 530 disposed to cover the substrate 510 (see fig. 5); and
a second layer 550 (partially) located in the first area and on the first layer 530.
Regarding claim 4, Huang discloses the semiconductor device according to claim 1, wherein the first dielectric layer 530 & 550 comprises:
a first layer 530 disposed on the substrate 510 and (partially) located in the first area; and
a second layer 550 covering the first layer 530 and covering the substrate 510 in the second area. See fig. 5.
Regarding claim 5, Huang discloses the semiconductor device according to claim 3, wherein a material of at least one of the first layer 530 or the second layer 550 comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See paras. 0032, 0046, 0051.
Regarding claim 6, Huang discloses the semiconductor device according to claim 4, wherein a material of at least one of the first layer or the second layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See paras. 0026, 0032, 0046, 0051.
Regarding claim 7, Huang discloses the semiconductor device according to claim 1, wherein the substrate 110 comprises:
a base 102 and an epitaxial layer 104 (paras. 0019, 0020, 0039), wherein the epitaxial layer 104 is disposed between the base 102 and the gate 560;
a material of the base 102 comprises one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, or sapphire (paras. 0019, 0039); and
a material of the epitaxial layer comprises one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, or scandium aluminum nitride (para. 0039).
Regarding claim 8, Huang discloses the semiconductor device according to claim 1, wherein a material of the gate 560 or the field plate 580 comprises at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, or copper. See para. 0027.
Regarding claim 9, Huang discloses the semiconductor device according to claim 1, wherein a material of the second dielectric layer 530 & 553 comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See para2. 0024, 0026.
Claim Rejections - 35 U.S.C. § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2019/0081154) in view of Hill et al. (US 2015/0144953).
Regarding claim 1, Watanabe discloses a semiconductor device, comprising:
a substrate 10 (see fig. ;
a first dielectric layer 20 having a first area (area vertically overlapped by gate electrode 23) and a second area (area vertically overlaps layers 18, 19) disposed outside of the first area, a first thickness of the first dielectric layer in the first area being greater than a second thickness of the first dielectric layer in the second area;
a gate 23, located on the substrate 10 in the first area, the gate comprising:
a first gate structure (portion of the gate 23 which is laterally surrounded by the first dielectric layer 20) penetrating the first area of the first dielectric layer 20 in a direction perpendicular to a surface of the substrate; and
a second gate structure (portion of the gate 23 which is formed on top of the first dielectric layer 20) contacting the first gate structure, wherein the second gate structure covers the first gate structure and covers a part of the first dielectric layer 20.
Watanabe fails to disclose:
a second dielectric layer covering the first gate and the first dielectric layer; and
a field plate having a part disposed on the second dielectric layer and that is disposed in both the first area and the second area.
Hill discloses:
a semiconductor device comprising:
a second dielectric layer (raised portion of dielectric layer 150 laterally surrounded by layer 170; see fig. 1) covering a first gate 140 and a first dielectric layer (flat portion of layer 150 that is in direct contact with layer 120; see also para. 0020 of Hill); and
a field plate 160 having a part disposed on the second dielectric layer and that is disposed in both the first area and the second area (see further para. 0021-0024 of Hill).
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Watanabe to further include a second dielectric layer and a field plate, as that/those taught by Hill, in order to improve device performance by reducing the peak electric field in the transistor. See para. 0002 of Hill.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 January 2, 2026