DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/18/2026.
Claims 1-9, and 20-21 are pending in this application.
Claims 10-19 have been cancelled.
Claim Objection
2. The claim is objected to for the following reason:
In claim 1, line 5, the term “the dielectric layer” lacks an antecedent basis. It should be read as – the first dielectric layer --.
In claim 1, line 16, the term “the first gate” lacks an antecedent basis. It should be read either as – the structure --.
Appropriate corrections are required.
Remarks
3. Applicant's arguments have been fully considered, but are moot in view of a new ground of rejection. See details below.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3-9, and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smorchkova et al. (US 2009/0108299)
Regarding claim 1, Smorchkova discloses a semiconductor device, comprising:
a substrate 205-230 (see fig. 2, and the Annotated Drawing below);
a first dielectric layer 240 (portion of dielectric layer 240 underneath a wider portion of gate structure 235) having a first area and a second area disposed outside of the first area, a first thickness of the first dielectric layer in the first area being greater than a second thickness of the first dielectric layer in the second area, wherein the (first) dielectric layer within the first area includes a gap (in which a first gate structure is located) defined therethrough, wherein portions of the first dielectric layer 240 within the first area are disposed on opposite sides of the gap and are symmetric with each other, and wherein the first dielectric layer within the second area includes a surface facing the substrate 205-230 and an opposing surface (interfacing with bottom surface of second field plate 250) facing away from the substrate 205-230 and defining a plane, and the plane intersects the first dielectric layer 240 within the first area;
a gate 235, located on the substrate in the first area, the gate comprising:
a first gate structure disposed through the gap in a direction perpendicular to a surface of the substrate, and
a second gate structure contacting the first gate structure, wherein the second gate structure covers the first gate structure and covers a part of the first dielectric layer;
a second dielectric layer (see the Annotated Drawing) covering the
a field plate 245 having a part disposed on the second dielectric layer and that is disposed in both the first area and the second area.
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Regarding claim 3, Smorchkova discloses the semiconductor device according to claim 1, wherein the first dielectric layer 240 comprises:
a first layer disposed to cover the substrate; and
a second layer located in the first area and on the first layer. See fig. 2.
Regarding claim 4, Smorchkova discloses the semiconductor device according to claim 1, wherein the first dielectric layer 240 comprises:
a first layer disposed on the substrate and located in the first area; and
a second layer covering the first layer and covering the substrate in the second area. See fig. 2.
Regarding claim 5, Smorchkova discloses the semiconductor device according to claim 3, wherein at least one of the first layer or a second sub-film layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See para. 0033.
Regarding claim 6, Smorchkova discloses the semiconductor device according to claim 4, wherein at least one of the first layer or a second sub-film layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See para. 0033.
Regarding claim 7, Smorchkova discloses the semiconductor device according to claim 1, wherein the substrate 205-230 comprises:
a base 205 and an epitaxial layer 210-220, wherein the epitaxial layer is disposed between the base 205 and the gate 235;
a material of the base comprises one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, or sapphire; and
a material of the epitaxial layer comprises one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, or scandium aluminum nitride. See paras. 0019, 0032, 0037.
Regarding claim 8, Smorchkova discloses the semiconductor device according to claim 1, wherein a material of the gate or the field plate comprises at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, or copper. See paras. 0023-0026, 0033-0035.
Regarding claim 9, Smorchkova discloses the semiconductor device according to claim 1, wherein a material of the second dielectric layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or titanium oxide. See para. 0033.
Regarding claim 20, Smorchkova discloses the semiconductor device according to claim 1, wherein the first dielectric layer 240 in the first area includes portions on opposite sides of the plane. See fig. 2.
Regarding claim 21, Smorchkova discloses the semiconductor device according to claim 1, wherein the gate is symmetric around a vertical axis. See fig. 2.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Smorchkova et al. (US 2009/0108299) in view of Huang et al. (US 2020/0176389).
Regarding claim 2, Smorchkova discloses the semiconductor device according to claim 1, comprising all claimed limitations, as discussed above, and further comprising:
a source 230, located in the substrate 205-230; and
a drain 225, located in the substrate, wherein the gate 235 is disposed between the source 230 and the drain 225;
wherein the part of the field plate 245 disposed on the second dielectric layer extends from the first area to the second area in a direction of the drain 225.
Smorchkova does not discloses wherein another part of the field plate 245 is located in the second area and is electrically connected to the source.
Huang discloses:
A semiconductor device comprising a source 540 (fig. 5, para. 0025), a drain 545, a gate electrode 560, and a field plate 580, wherein the field plate can be electrically connected to the source, to a ground potential, to the gate electrode, or to an arbitrary potential (see para. 0037).
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Smorchkova so that the field plate of Smorchkova can be electrically connected to the source, the gate, or to any arbitrary potential, as that taught by Huang. It would have been obvious that such electrical connection of the field plate would depend on the application of device and/or the choice of the designer, and it would involve only routine skills in the art. See further paras. 0033-0036 of Smorchkova.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/Dao H Nguyen/
Primary Examiner, Art Unit 2818
July 27, 2026
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