DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-12 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6, 8-12 and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amano (US 9748174 B1 hereinafter Amano ‘174).
With respect to Claim 1 Amano ‘174 discloses a microelectronic device (NAND device of exemplary structure with embodiment of 15A shown in Fig 1-15A and 16), comprising:
a stack structure (32/46, Fig 12, Col 23, Lines 59-63) comprising alternating conductive structures (468, Fig 15A, (46 comprises layers 462/464/466/468 as shown in Fig 15A and Col 23, Line 67 and Col 24 Lines 1-6)) and dielectric structures (32, Fig 12, Col 23, Line 62);
a memory pillar (55, Fig 15, Col 23, Lines 63-64) extending through (55 extending through 32/46 disclosed in Fig 15A and Fig 12) the stack structure (32/46) and defining memory cells (Fig 15A and Col 23, Lines 15-125 disclose memory cell at intersection of 55 and 46) at intersections of the memory pillar (55) and the conductive structures (468);
a boron-containing material (462, Fig 15A, Col 24, Lines 1-2 and Fig 16 (reference curve 1620), Col 25, Lines 12-24 and Col 25, Lines 53-65 disclose 462 as a boron-containing material) on horizontal surfaces (462 on horizontal surfaces of 32 disclosed in Fig 15A) of the dielectric structures (32) of the stack structure (32/46);
a liner material (466, Fig 15A, Col 24, Line 3) on the conductive structures (468)(layer 466 on 468 disclosed in Fig 15A) of the stack structure (32/46); and
a barrier material (464, Fig 15A, Col 24, Line 2) between (464 between 462 and 466 disclosed in Fig 15A and Col 23, Line 67 and Col 24 Lines 1-6) the boron-containing material (462) and the liner material (466).
With respect to Claim 3 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the boron- containing material (462) is on at least a portion of the memory pillar (55)(Fig 15A discloses layer 462 contacts layer 52 of memory pillar 55).
With respect to Claim 4 Amano ‘174 discloses all limitations of the microelectronic device of claim 3, and Amano ‘174 further discloses wherein the boron-containing material (462) directly contacts (Fig 15A discloses 462 directly contacts 52) a charge-blocking material (52, Fig 15A, Col 14, Lines 23-26) of the memory pillar (55).
With respect to Claim 6 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein horizontal surfaces of the boron-containing material (462) directly contact horizontal surfaces of the barrier material (464)(Fig 15A and Col 24, Line 1-6 discloses horizontal layers of 462 directly contact horizontal surfaces of 464).
With respect to Claim 8 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the liner material (466) and the barrier material (464) are between (Fig 15A discloses 466 and 464 between 462 and 468) the boron-containing material (462) and the conductive structures (468).
With respect to Claim 9 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the boron-containing material (462) comprises elemental boron, polymeric boron, a boron oxide material, a silicon boride material, a silicon boron oxide material, or a combination thereof (Col 25, Lines 58-60 and Fig 16 (reference exemplary structure curve 1620) disclose 462 comprises boron-10).
With respect to Claim 10 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the boron-containing material (462) separates the conductive structures (468) of the stack structure (32/46) from the dielectric structures (32) of the stack structure (32/46)(Fig 15A discloses 462 separates conductive structures 468 from dielectric structures 32).
With respect to Claim 11 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the boron-containing material (462) is present in an array region (100, Fig 14, Col 5, Line 53) of the microelectronic device (exemplary structure with embodiment of 15A shown in Fig 1-15A and 16)(Fig 15A is a section of array region 100 shown in Fig 14 which shows layer 46, therefore 462 (part of 46) is present in array region 100).
With respect to Claim 12 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 discloses further comprising a contact structure (76, Fig 15A, Col. 21, Lines 34-35) in a contact region (300, Fig 14, Col 5, Lines 54-57, discloses 76 straddles memory array 100 and contact region 300) of the stack structure (32/46), wherein the boron-containing material (462) is between sidewalls (Fig 15A discloses 462 is between sidewalls of 32/46 and 76) of the stack structure (32/46) and the contact structure (76).
With respect to Claim 21 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the liner material (466) directly contacts surfaces (Fig 15A discloses 466 directly contacts surfaces of 468) of the conductive structures (468) of the stack structure (32/46).
With respect to Claim 22 Amano ‘174 discloses all limitations of the microelectronic device of claim 1, and Amano ‘174 further discloses wherein the liner material (466) comprises at least one of a metal material and a metal nitride material (Col 24, Line 1 discloses 462 comprises a metallic nitride).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Amano ‘174 in view of Prakash et al. (US 2020/0258558 A1, hereinafter Prakash ‘558) in view of the following arguments.
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With respect to Claim 19 Amano ‘174 discloses a memory device (Memory device of exemplary structure with embodiment of 15A shown in Fig 1-15A and 16, Col 3, Lines 6-14, hereinafter MD), the memory device (MD) comprising a microelectronic device NAND device of exemplary structure with embodiment of 15A shown in Fig 1-15A and 16), comprising:
a stack structure (32/46, Fig 12, Col 23, Lines 59-63) comprising vertically alternating conductive structures (468, Fig 15A, (46 comprises layers 462/464/466/468 as shown in Fig 15A and Col 23, Line 67 and Col 24 Lines 1-6)) and dielectric structures (32, Fig 12, Col 23, Line 62);
a memory pillar (55, Fig 15, Col 23, Lines 63-64) extending through the stack structure (32/46) and
a boron-containing material (462, Fig 15A, Col 24, Lines 1-2 and Fig 16 (reference curve 1620), Col 25, Lines 12-24 and Col 25, Lines 53-65 disclose 462 as a boron-containing material) between the conductive structures (468) and the dielectric structures (32) of the stack structure (32/46), portions (vertical sidewalls of 462 as shown in Fig 15A) of the boron-containing material (462) separating the conductive structures (468) from the memory pillar (55)(Fig 15A discloses vertical ends of 462 separate 468 from 55);
a liner material (466, Fig 15A, Col 24, Line 3) between (466 between 462 and 468 disclosed in Fig 15A) the boron-containing material (462) and the conductive structures (468) of the stack structure (32/46); and
a barrier material (464, Fig 15A, Col 24, Line 2) having a first surface (top surface of 464 as shown in annotated Fig 15A of Amano ‘174) and a second surface (bottom surface of 464 as shown in annotated Fig 15A of Amano ‘174) opposite to the first surface (top surface of 464 opposite bottom surface of 464 disclosed in annotated Fig 15A of Amano ‘174), the first surface (top surface of 464 as shown in annotated Fig 15A of Amano ‘174) of the barrier material (464) in direct contact with (annotated Fig 15A of Amano ‘174 discloses top surface of 464 in direct contact with 462) the boron-containing material (462), and the second surface (bottom surface of 464 as shown in annotated Fig 15A of Amano ‘174) of the barrier material (464) in direct contact with (annotated Fig 15A of Amano ‘174 discloses bottom surface of 464 in direct contact with 466) the liner material (466).
But Amano ‘174 fails to explicitly disclose an electronic system, comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device.
Nevertheless, in a related endeavor (Fig 1A of Prakash ‘558), Prakash ‘558 teaches an electronic system (100/120/140, Fig 1A of Prakash ‘558, Para [0051-0052]), comprising: an input device (input of 140, Fig 1A of Prakash ‘558, Para [0063]); an output device (output of 140, Fig 1A of Prakash ‘558, Para [0063]); a processor device (122c, Fig 1A of Prakash ‘558, Para [0058]) operably coupled (Fig 1A and Para [0063] of Prakash ‘558 discloses processor coupled to input and output device) to the input device (input of 140) and the output device (output of 140); and a memory device (126, Fig 1A of Prakash ‘558, Para [0051]) operably coupled (Fig 1A of Prakash ‘558 discloses memory device coupled to processor) to the processor device (122c).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Prakash ‘558’s an electronic system, comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device into Amano ‘174’s device. Amano ‘174 teaches a NAND memory device and discloses peripheral devices connected to the memory device. Prakash ‘558 teaches a NAND memory device and further teaches a system coupled to the memory device. The ordinary artisan would have been motivated to modify Amano ‘174 in the manner set forth above, at least, because the details that Prakash ‘558 provides on coupling peripheral devices can reduce R&D time and costs that the person of ordinary skill in the art would need to spend to integrate the memory device into a functional device.
As incorporated, the input (input of 140), output (output of 140) and processor (122c) of Prakash ‘558 would be used with the memory device of Aman ‘174 to comprise a system.
With respect to Claim 20 Amano ‘174 as modified by Prakash ‘558 discloses all limitations of the electronic system of claim 19, and Amano ‘174 further discloses wherein the boron-containing material (462) directly contacts surfaces (Fig 15A discloses 462 directly contacts surfaces of 55) of the memory pillar (55) and dielectric structures (32) of the stack structure (32/46)(Fig 15A discloses 462 directly contacts surfaces of dielectric structures 32).
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 23: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “wherein the barrier material comprises at least one dielectric material” along with the rest of the limitations of said claims.
Closest prior art of record Amano (US 9.748,174 B1) teaches all limitations of independent Claim 1, however Amano (US 9.748,174 B1) fails to disclose “wherein the barrier material comprises at least one dielectric material”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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