Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 3/23/26 has been entered.
Response to Arguments
Applicant’s argument with regard to the amendment is not persuasive because it improperly compares the top of the combined gate stack 200A/202 rather than the claimed first and second portions of the first conductive layer.
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Examiner’s response: Applicant argues that Tailor fails to disclose the amended height limitation because layers 200A and 202 extend to the same height. This argument is not persuasive. Claim 1 does not require the upper gate electrode to extend higher than an entire conductive stack or higher than every portion of any conductive layer. Rather, claim 1 requires that “the upper gate electrode extends to a height that is higher than the first and second portions of the first conductive layer.”
In the rejection, the “first portion of the first conductive layer” corresponds to the horizontally extending conductive portion of 200A in region 144A, and the “second portion of the first conductive layer” corresponds to the horizontally extending conductive portion of 200A in region 146A, as shown in Fig. 9. Please refer to the attached annotated Fig. 9 of Tailor.
Figure 9 clearly shows upper gate electrode 202 extending vertically above both identified portions of conductive structure 200A. Therefore, Tailor discloses the claimed limitation requiring “the upper gate electrode extends to a height that is higher than the first and second portions of the first conductive layer.”
Applicant’s argument is further not commensurate with the scope of the claim because claim 1 does not require the upper gate electrode to extend higher than the entirety of the first conductive layer or higher than every conductive portion of conductive structure 200A. Accordingly, Tailor discloses every limitation of claim 1 arranged as claimed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tailor (US 20220302306).
Regarding claim 1. Fig 6 (shows an intermediate processing step of forming Fig 9), Fig 7 (shows an intermediate processing step of forming Fig 9) and Fig 9 of Tailor discloses A semiconductor device comprising:
Tailor discloses a semiconductor device in Figs. 6, 7, and 9 including a semiconductor substrate 104 ([0045]; see Fig. 7 for labeling) comprising an upper surface and a channel region located beneath the gate structure and between the source and drain regions in structure 144A. Tailor further discloses a source electrode contacting source region 168 and a drain electrode contacting drain region 154 in Fig. 9/144A, both overlying the semiconductor substrate.
Tailor further discloses one or more lower dielectric layers 132 and 136 disposed over the upper surface of the semiconductor substrate, and one or more intermediate dielectric layers 134 disposed over the one or more lower dielectric layers.
Tailor further discloses a multiple-part gate structure 200A/202 including a lower gate electrode 200A formed from a first portion of a first conductive layer ([0043], “metals”). The first portion of the first conductive layer includes a first segment corresponding to the lower vertical portion of 200A adjacent the channel region in Fig. 9, which extends through a first gate opening formed in dielectric layers 132/136 after removal of region 166 as shown in Figs. 6 and 7, over the channel region. The first portion of the first conductive layer further includes a second segment corresponding to the lateral upper portion of 200A extending rightward in Fig. 9, which overlies dielectric layers 132/136 and extends from the first gate opening toward the drain electrode.
Tailor further discloses an upper gate electrode 202 formed from a second conductive layer ([0043], “conductor layer”), wherein upper gate electrode 202 extends through intermediate dielectric layer 134 and contacts lower gate electrode 200A. In particular, Fig. 9 shows lower conductive portion 150 of upper gate electrode 202 extending through dielectric layer 134 into contact with conductive structure 200A.
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Tailor further discloses a lower field plate corresponding to the lateral drain-side conductive extension portion of conductive structure 200A in region 146A of Fig. 9, disposed between the lower gate electrode and the drain electrode, wherein the lower field plate is formed from a second portion of the first conductive layer 200A.
Further, Fig. 9 shows upper gate electrode 202 extending vertically above the first and second portions of conductive structure 200A. In the rejection, the “first portion of the first conductive layer” corresponds to the horizontally extending conductive portion of 200A in region 144A, and the “second portion of the first conductive layer” corresponds to the horizontally extending conductive portion of 200A in region 146A. Please refer to the attached annotated version of Fig. 9 of Tailor illustrating the examiner’s mapping of the recited first and second portions of the first conductive layer. Figure 9 clearly shows upper gate electrode 202 extending vertically above both identified portions of conductive structure 200A. Therefore, Tailor discloses the limitation “wherein the upper gate electrode extends to a height that is higher than the first and second portions of the first conductive layer.”
Accordingly, Tailor discloses every limitation of claim 1 arranged as claimed.
Regarding claim 2. Tailor discloses The semiconductor device of claim 1, wherein:
the second segment of the lower gate electrode and the lower field plate both are formed on the upper surface of the one or more lower dielectric layers (Fig 9), and a field plate-to-gate distance is defined as a distance between an edge of the second segment and an edge of the lower field plate (Fig 9).
Regarding claim 3. Tailor discloses The semiconductor device of claim 1, wherein:
the one or more lower dielectric layers include a first dielectric layer 132 disposed on the upper surface of the semiconductor substrate, and a second dielectric layer 136 disposed on the first dielectric layer (Fig 9).
Regarding claim 4. Tailor discloses The semiconductor device of claim 1, wherein:
the first conductive layer is formed from a metal stack of one or more Schottky materials selected from nickel, platinum, titanium, titanium nitride, tantalum nitride, copper, palladium, chromium, tungsten, iridium, and poly-silicon [0043], and
the second conductive layer is formed from one or more conductive materials selected from gold, silver, aluminum, copper, and titanium [0043].
Regarding claim 7. Tailor discloses The semiconductor device of claim 1, wherein:
the upper gate electrode has a cross-sectional shape selected from a symmetrical T-shape, an asymmetrical T-shape (Fig 9), and a trapezoidal shape.
Regarding claim 10. Tailor discloses The semiconductor device of claim 1, further comprising:
one or more upper dielectric layers 204 (refer to Fig 8 for detail label) disposed over the one or more intermediate dielectric layers and over the upper gate electrode (Fig 8); and
a conductive connection 164 that extends over the one or more upper dielectric layers and over the upper gate electrode to electrically connect the lower field plate to the source electrode (Fig 8, [0049]: via 212).
Allowable Subject Matter
Claims 5-6, 8-9 and 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a gate dielectric between the first segment of the lower gate electrode and the semiconductor substrate”.
Regarding claim 6, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the upper gate electrode has a T-shaped cross-section with a stem that extends through the one or more intermediate dielectric layers to contact the lower gate electrode, and first and second protruding regions that extend over portions of the upper surface of the one or more intermediate dielectric layers”.
Regarding claim 8, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “an upper field plate formed from the second conductive layer, the upper field plate has a T-shaped cross section with a stem that extends through the one or more intermediate dielectric layers to contact the lower field plate, and first and second protruding regions that extend over portions of the upper surface of the one or more intermediate dielectric layers”.
Regarding claim 11, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “forming a second gate opening through the one or more intermediate dielectric layers to expose the lower gate electrode”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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