DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on November 24th, 2025 is acknowledged. By virtue of this election, claims 1-8 are currently presented. Claims 9-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bando et al. (US 2019/0067251 A1; hereinafter Bando).
With respect to claim 1, Bando teaches a semiconductor device PM1 in at least Figs. 1-43, comprising:
a first semiconductor unit PK1 including a first semiconductor chip CT and a first substrate BSwa, the first substrate BSwa including, on a first main surface thereof, a first wiring board (of BSwa) to which the first semiconductor chip CT is bonded (see Fig. 22 and paragraphs 102, 103, 117, 130, 135, 184, 185, 187, 194);
a second semiconductor unit PK2 including a second semiconductor chip CT and a second substrate BSwb, the second substrate BSwb including, on a second main surface thereof, a second wiring board (of BSwb) to which the second semiconductor chip CT is bonded (see Fig. 22 and paragraphs 102, 103, 117, 130, 135, 184, 185, 187, 195);
a cooling unit CL2 having a first side (right side in Fig. 22) in a plan view of the semiconductor device PM1 and including a first cooling surface and a second cooling surface that are opposite to each other and respectively have thereon the first semiconductor unit PK1 facing the first substrate BSwa and the second semiconductor unit PK2 facing the second substrate BSwb so that the cooling unit CL2 is sandwiched between the first PK1 and second PK2 semiconductor units (see Fig. 22 and paragraphs 177-179, 184, 188, 192); and
an output terminal BSwd provided at the first side (right side in Fig. 22) of the cooling unit CL2 and being connected to both the first wiring board (of BSwa) and the second wiring board (of BSwb) (see Fig. 22 and paragraphs 184, 187-189, 194, 195, 197).
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest wherein the first semiconductor chip includes a first output electrode provided on a front surface thereof and a first input electrode provided on a rear surface thereof, the second semiconductor chip includes a second output electrode provided on a front surface thereof and a second input electrode provided on a rear surface thereof, the first wiring board includes first input wiring to which the rear surface of the first semiconductor chip is bonded and first output wiring that is adjacent to the first input wiring and is electrically connected to the first output electrode of the first semiconductor chip, the second wiring board includes second input wiring to which the rear surface of the second semiconductor chip is bonded and second output wiring that is adjacent to the second input wiring and is electrically connected to the second output electrode of the second semiconductor chip, and the output terminal connects the first input wiring to the second output wiring, as called for in claim 2 (claims 3-8 depend from claim 2).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because US 20060096299 A1 teaches a semiconductor device similar to that of the claimed invention.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893