DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 11/24/2025.
Claims 1-3, 5-8, 21-25, 27-31, 33, and 34 are pending in this application.
Claims 4, 9-20, 26, and 32 have been cancelled.
Remarks
2. Applicant's arguments have been fully considered, but are moot in view of a new ground of rejection. See details below.
Claim Rejections - 35 U.S.C. § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 21, 22, 25, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 9,349,703) in view of Harada et al. (US 2002/0005583)
Regarding claim 1, Chiu discloses a semiconductor packaging structure, comprising:
a die 126A (see fig. 1D) having a first (lower) surface, a second (upper) surface opposite the first surface, and sides, the die comprising a bond pad 104 on the first surface;
a mold compound 108c (see col. 3, lines 45-56) on the sides of the die and on the second surface of the die;
a first metal structure106 (in layer 108B) over the die 126A, the first metal structure 106 electrically coupled to the bond pad 104;
a first insulating material 108B around sides of the first metal structure 106;
a second metal structure 104 (in layer 108A) over at least a portion of the first metal structure 106 and over at least a portion of the first insulating material 108B, the second metal structure 104 electrically coupled to the first metal structure 106, wherein at least a portion the second metal structure 104 (in layer 108A) extends beyond an edge of the die 126A over the mold compound 108C; and
a second insulating material 108A around sides of the second metal structure 104.
Chiu fails to disclose:
the first metal structure including a first metal layer and a first barrier layer covering three sides of the first metal layer, wherein at least a portion of the first barrier layer is between the first metal layer and the bond pad; and
the second metal structure including a second metal layer and a second barrier layer covering three sides of the second metal layer, wherein at least a portion of the second barrier layer is between the first and second metal layers.
Harada discloses:
A package semiconductor device comprising:
a first metal structure 14 (see figs. 128, 130) including a first metal layer 14b & 14c and a first barrier layer 14a covering three sides of the first metal layer 14b/c, wherein at least a portion of the first barrier layer 14a is between the first metal layer 14b/c and a bond pad 10; and
the second metal structure 18 including a second metal layer 18b, 18c and a second barrier layer 18a covering three sides of the second metal layer 18b/c, wherein at least a portion of the second barrier layer 18a is between the first and second metal layers 14b/c, 18b/c.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chiu to further include barrier layers in the first and second metal structures, as that/those taught by Harada, in order to prevent diffusion of metal of the metal layers from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 21, Chiu discloses an apparatus comprising:
a first die 126A (see fig. 1D) having a first surface, a second surface opposite the first surface, and a side, the first die 126A comprising a conductive pad 104 on the first surface;
a second die 126B having a first surface, a second surface opposite the first surface, and a side, the side of the second die 126B facing the side of the first die 126A, the second die 126B comprising a conductive pad 104 on the first surface;
mold compound 108C (see col. 3, lines 45-56) over the second surface of the first die and over the second surface of the second die, at least a portion of the mold compound 108C between the side of the first die and the side of the second die;
a first metal segment 106 (in layer 108B) over the first die 126A, the first metal segment 106 electrically coupled to the conductive pad 104 on the first die;
a second metal segment 106 over the second die 126B, the second metal segment electrically coupled to the conductive pad 104 on the second die; and
an insulating material 108B over at least a portion of the first die 126A, at least a portion of the second die 126B, and at least a portion of the mold compound 108C, at least a portion of the insulating material 108B between the first metal segment and the second metal segment.
Chiu fails to disclose:
a first barrier layer covering three sides of the first metal segment 106, at least a portion of the first barrier layer being between the first metal segment 106 and the first die 126A; and
a second barrier layer covering three sides of the second metal segment 106, at least a portion of the second barrier layer being between the second metal segment 106 and the second die 126B.
Harada discloses:
An apparatus comprising:
a barrier layer 14a (see figs. 128, 130) covering three sides of a metal segment 14b & 14c electrically coupled to a bond pad 10 of a die 1 (die 1 comprising at least a semiconductor device, e.g. at least a transistor 6; see also para. 0033 of the pending application), at least a portion of the barrier layer 14a being between the metal segment 14b/c and the die 1.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chiu to further include barrier layers in the metal segments, as that/those taught by Harada, in order to prevent diffusion of metal of the metal layers from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 22, Chiu/Harada discloses the apparatus of claim 21, wherein the insulating material 108B (in Chiu) is a first insulating material, the apparatus further comprising:
a third metal segment 104 (in layer 108A of Chiu) over the first metal segment 106 (in layer 108B), the third metal segment 104 electrically coupled to the first metal segment 106;
a third barrier layer 18a (in Harada) covering three sides of a third metal segment 18c; and
a second insulating material 108A (in Chiu) or 15 (in Harada) around the third metal segment. See fig. 1D of Chiu, and fig. 130 of Harada.
Regarding claim 25, Chiu/Harada discloses the apparatus of claim 22, further comprising a plate layer 104 (in layer 112) over the second insulating material and the third metal segment 104, the plate layer 104 including a solderable material (inherently via solder balls 110, see fig. 1D in Chiu).
Regarding claim 27, Chiu discloses an apparatus comprising:
a die 126A (see fig. 1D) having a first surface, a second surface opposite the first surface, and sides, the die comprising a conductive pad 104 on the first surface;
a mold compound 108C (see col. 3, lines 45-56) around the sides of the die and on the second surface of the die;
a metal segment 106 (in layer 108B) over the conductive pad 104, the metal segment electrically coupled to the conductive pad;
an insulating material 108B over at least a portion of the die 126A and around the metal segment 106.
Chiu fails to disclose:
a barrier layer covering three sides of the metal segment 106, the barrier layer being between the metal segment 106 and the conductive pad 104.
Harada discloses:
A apparatus comprising:
a barrier layer 14a (see figs. 128, 130) covering three sides of a metal segment 14b & 14c electrically coupled to a conductive pad 10 of a die 1 (die 1 comprising at least a semiconductor device, e.g. at least a transistor 6; see also para. 0033 of the pending application), the barrier layer 14a being between the metal segment 14b/c and the conducive pad 10.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chiu to further include a barrier layer, as that taught by Harada, in order to prevent diffusion of metal of the metal segment from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 28, Chiu/Harada discloses the apparatus of claim 27, wherein the metal segment 106 (in Chiu) is a first metal segment, the barrier layer 14a (in Harada) is the first barrier layer, the insulating material 108B is a first insulating material, and the apparatus further comprises:
a second metal segment 104 (in layer 108A of Chiu) or metal segment 18b & 18c (in Harada) over the first metal segment, the second metal segment electrically coupled to the first metal segment;
a second barrier layer 18a (fig. 130 of Harada) covering three sides of the second metal segment 18b/c, at least a portion of the second barrier layer 18a being between the first and second metal segments 14b/c, 18b/c; and
a second insulating material 108A (in Chiu) or 15 (in Harada) over at least a portion of the first insulating material and around the second metal segment;
a plate layer 104 (in layer 112 of Chiu) over the insulating material and over second metal segment 104, the plate layer 104 including a solderable material (inherently via solder balls 110, see fig. 1D of Chiu).
5. Claims 1-3, 5-8, 21-25, 27-31, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Hizume et al. (US 8,153,479) in view of Harada et al. (US 2002/0005583)
Regarding claim 1, Hizume discloses a semiconductor packaging structure, comprising:
a die 27 (see fig. 12) having a first (lower) surface, a second (upper) surface opposite the first surface, and sides, the die comprising a bond pad 26 on the first surface;
a mold compound 29 on the sides of the die and on the second surface of the die 27;
a first metal structure 31 or 31 & 32 on the die, the first metal structure electrically coupled to the bond pad 26;
a first insulating material 21 and/or 33 around sides of the first metal structure 31 or 31 & 32;
a second metal structure 32 and/or 34 over at least a portion of the first metal structure 31 or 31 & 32 and over at least a portion of the first insulating material 21/33, the second metal structure 32/34 electrically coupled to the first metal structure 31 / 32, wherein at least a portion the second metal structure 32/34 extends beyond an edge of the die 27 over the mold compound 29; and
a second insulating material 33 and/or 35 around sides of the second metal structure 32/34.
Hizume fails to disclose:
the first metal structure including a first metal layer and a first barrier layer covering three sides of the first metal layer, wherein at least a portion of the first barrier layer is between the first metal layer and the bond pad; and
the second metal structure including a second metal layer and a second barrier layer covering three sides of the second metal layer, wherein at least a portion of the second barrier layer is between the first and second metal layers.
Harada discloses:
A package semiconductor device comprising:
a first metal structure 14 (see figs. 128, 130) including a first metal layer 14b & 14c and a first barrier layer 14a covering three sides of the first metal layer 14b/c, wherein at least a portion of the first barrier layer 14a is between the first metal layer 14b/c and a bond pad 10; and
the second metal structure 18 including a second metal layer 18b, 18c and a second barrier layer 18a covering three sides of the second metal layer 18b/c, wherein at least a portion of the second barrier layer 18a is between the first and second metal layers 14b/c, 18b/c.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hizume to further include barrier layers in the first and second metal structures, as that/those taught by Harada, in order to prevent diffusion of metal of the metal layers from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 2, Hizume/Harada discloses the semiconductor packaging structure of claim 1, wherein the first insulating material and the second insulating material are composed of a photosensitive material. See col. 2, lines 24-45; col. 4, lines 25-38; col. 8, lines 50-63 of Hizume.
Regarding claim 3, Hizume/Harada discloses the semiconductor packaging structure of claim 2, wherein the photosensitive material is a permanent photoresist. See col. 2, lines 24-45; col. 4, lines 25-38; col. 8, lines 50-63 of Hizume.
Regarding claim 5, Hizume/Harada discloses the semiconductor packaging structure of claim 1, further comprising:
a plate layer 35 and/or 37 over the second insulating material and on the second metal structure 34. See Hizume.
Regarding claim 6, Hizume/Harada discloses the semiconductor packaging structure of claim 5, wherein the plate layer 35/37 extends beyond a top surface of the second insulating material 33 or 35. See fig. 12 of Hizume.
Regarding claim 7, Hizume/Harada discloses the semiconductor packaging structure of claim 1, wherein the die 27 is a first die, the bond pad 26 is a first bond pad, the semiconductor packaging structure further comprising:
a second die 27 comprising a second bond pad 26; and
a third metal layer structure 31 or 31 & 32 over the second die 27, the third metal layer structure 31 or 31 & 32 electrically coupling the second bond pad 26 to the second metal structure 32 and/or 34, wherein the second metal structure 32/34 is over at least a portion of the first die and over at least a portion of the second die 27. See fig. 12 of Hizume.
Regarding claim 8, Hizume/Harada discloses the semiconductor packaging structure of claim 7, wherein the mold compound 29 at least partially surrounds the first die and the second die 27. See fig. 12.
Regarding claim 21, Hizume discloses an apparatus comprising:
a first die 27 (see fig. 12) having a first (lower) surface, a second (upper) surface opposite the first surface, and a side, the first die 27 comprising a conductive pad 26 on the first surface;
a second die 27 having a first (lower) surface, a second (upper) surface opposite the first surface, and a side, the side of the second die 27 facing the side of the first die 27, the second die 27 comprising a conductive pad 26 on the first surface;
mold compound 29 over the second surface of the first die 27 and over the second surface of the second die 27, at least a portion of the mold compound 29 between the side of the first die and the side of the second die;
a first metal segment 31 or 31 & 32 over the first die 27, the first metal segment electrically coupled to the conductive pad 26 on the first die;
a second metal segment 31 or 31 & 32 over the second die 27, the second metal segment electrically coupled to the conductive pad 26 on the second die; and
an insulating material 21 and/or 33 over at least a portion of the first die 27, at least a portion of the second die 27, and at least a portion of the mold compound 29, at least a portion of the insulating material 21/33 between the first metal segment 31 or 31 & 32 and the second metal segment 31 or 31 & 32.
Hizume fails to disclose:
a first barrier layer covering three sides of the first metal segment 106, at least a portion of the first barrier layer being between the first metal segment 106 and the first die 126A; and
a second barrier layer covering three sides of the second metal segment 106, at least a portion of the second barrier layer being between the second metal segment 106 and the second die 126B.
Harada discloses:
A package semiconductor device comprising:
a barrier layer 14a (see figs. 128, 130) covering three sides of a metal segment 14b & 14c electrically coupled to a bond pad 10 of a die 1 (die 1 comprising at least a semiconductor device, e.g. at least a transistor 6; see also para. 0033 of the pending application), at least a portion of the barrier layer 14a being between the metal segment 14b/c and the die 1.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chiu to further include barrier layers in the metal structures, as that/those taught by Harada, in order to prevent diffusion of metal of the metal layers from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 22, Hizume/Harada discloses the apparatus of claim 21, wherein the insulating material 21/23 is a first insulating material, the structure further comprising:
a third metal segment 32 and/or 34 over the first metal segment 31/32, the third metal segment electrically coupled to the first metal segment; and
a second insulating material 33 or 35 around the third metal segment. See fig. 12 of Hizume.
Regarding claim 23, Hizume/Harada discloses the apparatus of claim 22, further comprising a fourth metal segment 32/34 over the second metal segment 31/32, the fourth metal segment electrically coupled to the second metal segment, wherein the second insulating material 33/35 is around the fourth metal segment. See fig. 12 of Hizume.
Regarding claim 24, Hizume/Harada discloses the apparatus of claim 23, wherein the fourth metal segment is over the second metal segment, the fourth metal segment electrically coupling the first metal segment and the second metal segment. See fig. 12 of Hizume.
Regarding claim 25, Hizume/Tsai discloses the apparatus of claim 22, further comprising a plate layer 35 or 37 over the second insulating material and the third metal segment 34, the plate layer attaching the structure to a printed circuit board (PCB) 39. See fig. 10, 12, and col. 7, lines 28-37 of Hizume.
Regarding claim 27, Hizume discloses an apparatus comprising:
a die 27 (see fig. 12) having a first (lower) surface, a second (upper) surface opposite the first surface, and sides, the die 27 comprising a conductive pad 26 on the first surface;
a mold compound 29 around the sides of the die 27 and on the second surface of the die;
a metal segment 31 & 32 over the conductive pad 26, the metal segment electrically coupled to the conductive pad 26;
an insulating material 21 or 21 & 33 over at least a portion of the die 27 and around the metal segment 31 & 32.
Hizume fails to disclose:
a barrier layer covering three sides of the metal segment 106, the barrier layer being between the metal segment 106 and the conductive pad 104.
Harada discloses:
A apparatus comprising:
a barrier layer 14a (see figs. 128, 130) covering three sides of a metal segment 14b & 14c electrically coupled to a conductive pad 10 of a die 1 (die 1 comprising at least a semiconductor device, e.g. at least a transistor 6; see also para. 0033 of the pending application), the barrier layer 14a being between the metal segment 14b/c and the conducive pad 10.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Chiu to further include a barrier layer, as that taught by Harada, in order to prevent diffusion of metal of the metal segment from diffusing into the surrounding materials, thereby to reduce leakage, hence to increase the performance of the device.
Regarding claim 28, Hizume/Harada discloses the apparatus of claim 27,
wherein the metal segment 31 & 32 (in Hizume) is a first metal segment, the barrier layer 14a (in Harada) is the first barrier layer, the insulating material 21/33 is a first insulating material, and the apparatus further comprises:
a second metal segment 32 /34 or metal segment 18b & 18c (in Harada) over the first metal segment, the second metal segment electrically coupled to the first metal segment;
a second barrier layer 18a (fig. 130 of Harada) covering three sides of the second metal segment 18b/c, at least a portion of the second barrier layer 18a being between the first and second metal segments 14b/c, 18b/c; and
a second insulating material 33/35 (in Hizume) or 15 (in Harada) over at least a portion of the first insulating material and around the second metal segment;
a plate layer 35 or 37 over the second insulating material and over the second metal segment 32/34, the plate layer 35/37 including a solderable material. See fig. 12 of Hizume.
Regarding claim 29, Hizume/Harada discloses the apparatus of claim 27, wherein the die 27 is a first die, the apparatus further comprising:
a second die 27 having a first (upper) surface, a second (lower) surface opposite the first surface, and sides connecting the first surface and the second surface, the second die 27 comprising a conductive pad 26 on the first surface, the mold compound 29 on the second surface of the second die 27 and around the sides of the die, at least a portion of the mold compound 29 between the first die and the second die; and
a third metal segment 31 or 31 & 32 over the conductive pad 26 of the second die 27, the first insulating material 21/33 around the third metal segment. See fig. 12 of Hizume.
Regarding claim 30, Hizume/Harada discloses the apparatus of claim 29, wherein the second metal segment is over at least a portion of the mold compound and at least a portion of the third metal segment, the second metal segment electrically coupled to the third metal segment. See fig. 12.
Regarding claim 31, Hizume/Harada discloses the apparatus of claim 30, further comprising a fourth metal segment 32 and/or 34 over the third metal segment, the fourth metal segment electrically coupled to the third metal segment, the second insulating material around the fourth metal segment. See fig. 12.
Regarding claim 33, Hizume/Harada discloses the packaged semiconductor device of claim 1, wherein each of the first and second barrier layers includes at least one of: titanium, a titanium alloy, tantalum, or a tantalum alloy. See para. 0015 of Harada.
Regarding claim 34, Hizume/Harada discloses the packaged semiconductor device of claim 1, wherein each of the first and second metal layers includes copper. See col. 3, lines 39-46 of Hizume, and para. 0015 of Harada.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/Dao H Nguyen/
Primary Examiner, Art Unit 2818
January 24, 2026