DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-56 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Murakami (PG Pub. No. US 2020/0381302 A1) in view of Kamimura (Foreign patent no. JP 2015-046555 A, machine translation provided) and Ueda et al. (PG Pub. No. US 2005/0272224 A1).
Regarding claim 1, Murakami teaches a manufacturing method of a semiconductor device, comprising:
preparing a semiconductor substrate (¶ 0028: 1) having a plurality of element regions (¶ 0028 & fig. 1: device patterns 2) and having a first surface and a second surface opposite to each other (fig. 1: 1 has opposing top and bottom surfaces);
forming a crack (¶ 0049: VC) extending in a thickness direction of the semiconductor substrate along a boundary between the plurality of element regions (fig. 3: VC extends in thickness direction of 1 in boundary between device patterns 2) by pressing a pressing member (¶ 0037: 102) against the first surface of the semiconductor substrate along the boundary (fig. 3: 1 pressed against first surface of 1 along boundary between 2);
forming a metal film (¶ 0027: 3) over the plurality of element regions on the first surface of the semiconductor substrate (fig. 1: 3 formed over regions 2 on top surface of 1); and
dividing the semiconductor substrate and the metal film along the boundary (¶ 0065 & fig. 6: 1 and 3 divided along boundaries between die regions 2) by pressing a dividing member (¶ 0054: 202) against the semiconductor substrate along the boundary from a direction facing the second surface of the semiconductor substrate after the forming of the metal film (fig. 6: 202 pressed against opposite surface of 1 along boundaries between die regions 2 after forming 3).
Murakami does not teach the preparing including thinning the semiconductor substrate to the first surface, or forming a metal film after the forming of the crack.
Kamimura teaches a method of manufacturing a semiconductor device, including forming a crack (p. 3 line 1: cracks of scribe line S) extending in a thickness direction of a semiconductor substrate (fig. 2a: S extends in a thickness direction of wafer W) along a boundary between the plurality of element regions (figs. 1-2: S formed along scheduled cutting line L between chips W1) by pressing a pressing member (page 3 line 9: 10) against the first surface of the semiconductor substrate along the boundary (p. 3 lines 9-10 & fig. 2a: 10 pressed against top surface of W along cutting line L), the surface absent a metal film (fig. 2a: 10 pressed directly on surface of W); and
dividing the semiconductor substrate along the boundary by pressing a dividing member (p. 3 line 20: break bar 5) against the semiconductor substrate along the boundary from a direction facing the second surface of the semiconductor substrate (fig. 2d: 5 pressed against opposite surface of W along boundaries between circuit regions).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Murakami to include pressing the pressing member before forming the metal film, as a means to optimize the depth of the crack, and allow for a substrate thinning process (Kamimura, p. 3 lines 14-18, figs. 2b-2c), allowing for semiconductor devices with low power and high integration (Kamimura, p. 1 lines 19-20) as well as reducing defects such as chipping (Kamimura, p. 4 lines 1-7).
Murakami in view of Kamimura does not teach the preparing including thinning the semiconductor substrate to the first surface.
Ueda teaches a method of dividing a semiconductor substrate (¶ 0010: 7) along a boundary (15), the method including thinning the semiconductor substrate to a first surface (¶ 0010: surface of 7 polished), and forming a crack (¶ 0011: 18) extending in a thickness direction of the semiconductor substrate along the boundary (fig. 1B: 18 formed in thickness direction of 7) by pressing a pressing member (¶ 0011: 17) against the first surface of the semiconductor substrate along the boundary (fig. 1B: 17 pressed against polished surface of 7 along boundary 15).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the preparation of Murakami in view of Kamimura to include thinning the first surface, as a means to minimize the thickness for forming a crack suitable to divide the substrate.
Regarding claim 2, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, wherein
the pressing member is a scribing wheel (Murakami, ¶ 0037 and/or Kamimura, p. 3 line 2),
the pressing of the pressing member includes rolling of the scribing wheel (Murakami, ¶ 0048: 102 rotated along surface of 1, and/or Kamimura, p. 3 line 9: 10 is rolled on the surface of W), and
the forming of the crack includes forming, on the first surface, a scribe line with the crack extending in the thickness direction of the semiconductor substrate along the boundary (Murakami, fig. 3: VC formed on top surface of 1 extending in thickness direction along boundary between 2, and/or Kamimura, fig. 1a: cracks of S formed on top surface of W extending in the thickness direction along division line L).
Regarding claim 3, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, further comprising:
attaching a support plate (Murakami. ¶ 0037: stage 101) to the second surface before the forming of the crack (Murakami, fig. 2: 101 attached to bottom surface of 1 before forming VC); and
detaching the support plate from the second surface after the forming of the metal film and before the dividing of the semiconductor substrate and the metal film (Murakami, fig. 5: 101 detached from 1 after forming 3 and before dividing 1 and 3).
Regarding claim 4, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 3, further comprising
attaching a dicing tape (Murakami, ¶ 0061: protection film 5) to a surface of the metal film after the forming of the metal film (Murakami, fig. 5: 5 attached to surface of 3 after forming 3).
Murakami further teaches the metal film surface is exposed before detaching of the support plate (fig. 3).
Murakami is silent to attaching the dicing tape to a surface of the metal film before the detaching of the support plate.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to attaching the dicing tape to a surface of the metal film before the detaching of the support plate, in order to provide conformal adhesion to exposed top and side surfaces of 1/3, prior to placement on holding part 201 (Murakami, fig. 5).
Regarding claim 5, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, further comprising
covering the second surface with a protective member (Murakami, ¶ 0042: 4) before the dividing of the semiconductor substrate and the metal film (Murakami, fig. 5: 4 covers opposing surface of 1 before dividing 1/3 along lines SL), wherein
the dividing of the semiconductor substrate and the metal film includes pressing the dividing member against the semiconductor substrate along the boundary from the direction facing the second surface via the protective member (Murakami, ¶ 0062 & fig. 5: dividing 1 and 3 includes pressing 202 against 1 along boundary lines SL from direction facing surface of 1 via 4).
Regarding claim 6, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, further comprising:
disposing a main structure (Murakami, ¶ 0029: 2b) on the second surface prior to the forming of the crack (Murakami, fig. 2: 2b formed on opposing surface of 1 prior to forming VC).
Regarding claim 9, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, wherein the metal film is formed so as to cover substantially an entirety of the first surface (Murakami, fig. 2: 3 formed to at least indirectly cover entire surface of 2a/2b).
Regarding claim 10, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, wherein the dividing forms the semiconductor device in which the metal film functions as an electrode of the semiconductor device (Murakami, ¶ 0031: 3 comprises electrode material).
Regarding claim 11, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, wherein in the dividing, the metal film is divided together with the semiconductor substrate by the pressing of the dividing member (Murakami, ¶ 0051 & fig. 4: 3 divided together with 1 by pressing 102).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Murakami in view of Kamimura and Ueda as applied to claim 1 above, and further in view of Nakanishi et al. (PG Pub. No. US 2017/0032968 A1).
Regarding claim 7, Murakami in view of Kamimura and Ueda teaches the manufacturing method according to claim 1, including thinning of the semiconductor substrate to the first surface (Ueda, ¶ 0010).
Murakami in view of Kamimura and Ueda fails to teach the method further comprising:
attaching a support plate to the second surface before the thinning of the semiconductor substrate to the first surface.
Nakanishi teaches a method including thinning of a semiconductor substrate to a first surface (¶ 0032: second surface 14 of semiconductor substrate 11 is mechanically ground and polished, so that the thickness of the substrate reaches a suitable thickness) after attaching a support plate to a second opposing surface (¶ 0032: during grinding/polishing, first substrate surface 13 affixed to a support plate).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the thinning of Murakami in view of Kamimura and Ueda with a support plate attached to the second surface, as a means to protect the first surface during the thinning process (Nakanishi, ¶ 0032).
Regarding claim 8, Murakami in view of Kamimura, Ueda and Nakanishi teaches the manufacturing method according to claim 7, further comprising:
peeling the support plate off from the second surface (Nakanishi, ¶ 0033: support plate removed to expose first surface of substrate 11) before the dividing of the semiconductor substrate (Ueda, fig. 1B: 7 divided by pressing 17 and/or Murakami, ¶ 0065 & fig. 6: 1 divided by pressing 202).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818