DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on page 8 of the REMARKS, “Specifically, Nishioka et al. refers to Figs. 3(B) to 3(D) and describes a semi-additive method in which a conductive layer (58A) is formed of an electroless copper-plated film (52) and an electrolytic copper-plated film (56) such that the electrolytic copper-plated film (56) is formed to give the conductive layer (58A) the thickness 15 to 20 µm and then a copper-plating resist (54) is removed. Thus, the electrolytic copper-plated film (56) of Nishioka et al. does not disclose or suggest a portion formed in excess that is subjected to CMP.” The Office respectfully disagrees. Firstly, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The polished surface is being taught in view of the secondary Yamazaki reference. Secondly, “formed by chemical mechanical polishing” as currently amended does not represent product structure but only refers to the process by which the surface is formed. Thus the claim is a product claim that recites a process step(s) of chemical mechanical polishing and is thus treated as a product-by-process claim. See MPEP 2113. Lastly, as the semi-additive process discussed by Nishioka does not structurally limit the plating 56 being formed vertically. Thus if the manufacturer desires a precise height for the conductive pattern, the option of polishing 56 and 54 could be achieved a more precise and even height across the pattern using the means as taught in view of Yamazaki.
Applicant also argues on page 8 of the REMARKS, “Yamazaki et al. refers to Fig. 2C and describes that the substrate surface is polished to make the conductive pattern (2) and the plated resist pattern (8) flush with each other simply by mechanical polishing process. Yamazaki et al. does not disclose or suggest subjecting the conductive pattern (2) and the plated resist pattern (8) to CMP which utilizes both a chemical reaction and mechanical abrasion rather than solely relying on mechanical forces of mechanical polishing. CMP creates a surface with an extremely higher degree of flatness and smoothness than that of a mechanical polishing process which causes physical damages and leaves imperfections. Indeed, Yamazaki et al. describes a process simply to level the heights of the conductive pattern (2) and the plated resist pattern (8) with each other and does not teach or suggest achieving superior high-frequency transmission characteristics for fine wiring patterns with higher aspect ratios”. The Office respectfully disagrees. As stated previously, “formed by chemical mechanical polishing” as currently amended does not represent product structure but only refers to the process by which the surface is formed. Thus the claim is a product claim that recites a process step(s) of chemical mechanical polishing and is thus treated as a product-by-process claim. See MPEP 2113. Note also that Nishioka already teaches the structure meeting the claimed “higher aspect ratios”. The structure of a polished surface is taught in view of Nishioka in view of Yamazaki and structurally meets the language of the claim. Therefore the rejection stands.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4 – 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nishioka (US 2015/0163901 A1) in view of Yamazaki (US 2007/0126108 A1).
Regarding Claim 1, Nishioka (US 2015/0163901 A1) discloses a wiring substrate (Fig 1), comprising: an insulating layer (50B; [0018]); a first conductor layer (58B; [0019-0020]) formed on the insulating layer (50B) and including a first wiring (one 58B as seen in Fig 1(C)) and a second wiring (another and adjacent 58B as seen in Fig 1(C); [0019-0020]) formed adjacent to the first wiring; and a second conductor layer (58A) on an opposite side with respect to first conductor layer (58B) such that the insulating layer (50B) is covering the second conductor layer (58A), wherein the first conductor layer (58B) is formed such that each of the first wiring and the second wiring has an aspect ratio ([0022]; line width from 3 μm to 10 μm; [0035,0040]; thickness of 58A or 58B is 15 μm to 20 μm; e.g. a thickness of 20 μm to width of 5 μm [Wingdings font/0xE0] aspect ratio of 4; note that the claim language nor specification defines this “aspect ratio”) in a range of 2.0 to 4.0 ([0022]; line width from 3 μm to 10 μm; [0035,0040]; thickness of 58A or 58B is 15 μm to 20 μm; e.g. a thickness of 20 μm to width of 10 μm [Wingdings font/0xE0] aspect ratio of 2) and a wiring width of 5 μm or less ([0022]; line width from 3 μm to 10 μm) and that the first wiring and the second wiring are separated by a distance of 7 μm or less ([0022]; line space width from 3 μm to 10 μm), and the first conductor layer (58B) includes a seed layer (52; [0019-0031]) formed on the insulating layer (50B), and an (electrolytic plating) film (56; [0019-0031]) formed on the seed layer (52) such that the seed layer (52) is formed on a lower surface (as seen in Fig 1, 52 is only on a lower surface of 56 and not on a side surface of 56) of the (electrolytic) plating film (56) and not on a side surface of the (electrolytic) plating film (56) and that the (electrolytic) plating film (56) has an upper surface (upper surface of 56) on an opposite side with respect to the lower surface (lower surface of 56).
Nishioka does not explicitly disclose that the (electrolytic) plating film has a (polished) upper surface (formed by chemical mechanical polishing) on an opposite side with respect to the lower surface.
Yamazaki (US 2007/0126108 A1) teaches of a wiring substrate (Fig 2), comprising: an insulating layer (1; [0035]); a first conductor layer (layer with 3) formed on the insulating layer (1) and including a first wiring (3) and a second wiring (another and adjacent 3 as seen in Fig 2) formed adjacent to the first wiring; and the first conductor layer (3) includes a seed layer (7; [0039]) formed on the insulating layer (1), and an (electrolytic plating) film (2; [0039]) formed on the seed layer (7) such that the seed layer (7) is formed on a lower surface (as seen in Fig 2, 7 is only on a lower surface of 2 and not on a side surface of 2) of the (electrolytic) plating film (2) and not on a side surface of the (electrolytic) plating film (2) and that the (electrolytic) plating film (2) has a (polished [0039-0040]) upper surface on an opposite side with respect to the lower surface.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as disclosed by Nishioka, wherein the (electrolytic) plating film has a (polished) upper surface on an opposite side with respect to the lower surface as taught by Yamazaki, in order to make the conductive pattern and resist be flush with one another and control the height variance of layers or components atop, reduce variance of a quantity of material applied at a later manufacturing step, and reduce problems related to thickness (Yamazaki, [0005-0008]). The combination of Nishioka in view of Yamazaki would teach of a means to better control overall height of the assembly of the substrate and mounted components.
Claim states a “electrolytic plating film” but “electrolytic plating” does not represent product structure but only refers to the process by which the film is formed. Thus the claim is a product claim that recites a process step(s) of plating and is thus treated as a product-by-process claim. See MPEP 2113.
Claim states a “polished upper surface formed by chemical mechanical polishing” but “polished” and “chemical mechanical polishing” does not represent product structure but only refers to the process by which the surface is formed. Thus the claim is a product claim that recites a process step(s) of chemical mechanical polishing and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 2, Nishioka further discloses the wiring substrate (Fig 1) according to claim 1, further comprising: a first via conductor (60B; [0019-0022]) comprising the (electrolytic plating) film (56 of 60B) filling in a through hole (53) in the insulating layer (50B) such that the via conductor (60B) is connecting ([0019]) the first conductor layer (58B) and the second conductor layer (58A).
Claim states a “electrolytic plating film” but “electrolytic plating” does not represent product structure but only refers to the process by which the film is formed. Thus the claim is a product claim that recites a process step(s) of plating and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 4, Nishioka further discloses the wiring substrate (Fig 1) according to claim 1, wherein the first conductor layer (58B) has a thickness in a range of 7 μm to 20 μm ([0035,0040]; thickness of 58A or 58B is 15 μm to 20 μm).
Regarding Claim 5, Nishioka further discloses the wiring substrate (Fig 1) according to claim 1, wherein the seed layer includes a (sputtering) film (52).
Claim states a “sputtering film” but “sputtering” does not represent product structure but only refers to the process by which the film is formed. Thus the claim is a product claim that recites a process step(s) of sputtering and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 6, Nishioka further discloses the wiring substrate (Fig 1) according to claim 2, wherein the first conductor layer (58B) has a thickness in a range of 7 μm to 20 μm ([0035,0040]; thickness of 58A or 58B is 15 μm to 20 μm).
Regarding Claim 7, Nishioka further discloses the wiring substrate (Fig 1) according to claim 2, wherein the seed layer includes a (sputtering) film (52).
Claim states a “sputtering film” but “sputtering” does not represent product structure but only refers to the process by which the film is formed. Thus the claim is a product claim that recites a process step(s) of sputtering and is thus treated as a product-by-process claim. See MPEP 2113.
Regarding Claim 10, Nishioka further discloses the wiring substrate (Fig 1) according to claim 1, wherein the first conductor layer (58B) (is formed by forming the seed layer on the insulating layer (50B), forming a plating resist on the seed layer (52), forming the electrolytic plating film (56) on part of the seed layer (52) exposed from the plating resist such that the electrolytic plating film (56) has a thickness larger than a thickness of the plating resist, and polishing the electrolytic plating film (56) and the plating resist such that the thickness of the electrolytic plating film (56) and the thickness of the plating resist are reduced).
Claim states a “the first conductor layer is formed by forming the seed layer on the insulating layer, forming a plating resist on the seed layer, forming the electrolytic plating film on part of the seed layer exposed from the plating resist such that the electrolytic plating film has a thickness larger than a thickness of the plating resist, and polishing the electrolytic plating film and the plating resist such that the thickness of the electrolytic plating film and the thickness of the plating resist are reduced” but “the first conductor layer is formed by forming the seed layer on the insulating layer, forming a plating resist on the seed layer, forming the electrolytic plating film on part of the seed layer exposed from the plating resist such that the electrolytic plating film has a thickness larger than a thickness of the plating resist, and polishing the electrolytic plating film and the plating resist such that the thickness of the electrolytic plating film and the thickness of the plating resist are reduced” does not represent product structure but only refers to the process by which the films and seed and wiring are formed. Thus the claim is a product claim that recites a process step(s) of formed by forming the seed layer on the insulating layer, forming a plating resist on the seed layer, forming the electrolytic plating film on part of the seed layer exposed from the plating resist such that the electrolytic plating film has a thickness larger than a thickness of the plating resist, and polishing the electrolytic plating film and the plating resist such that the thickness of the electrolytic plating film and the thickness of the plating resist are reduced, and is thus treated as a product-by-process claim. See MPEP 2113.
Claim(s) 3, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishioka (US 2015/0163901 A1) in view of Yamazaki (US 2007/0126108 A1) as applied to claim 3 above and further in view of En (US 2004/0134682 A1).
Regarding Claim 3, Nishioka in view of Yamazaki teaches the limitations of the preceding claim.
Nishioka does not explicitly disclose the wiring substrate according to claim 2, wherein the via conductor has an aspect ratio in a range of 0.5 to 1.0.
En (US 2004/0134682 A1) teaches of a wiring substrate ([0386-0388]; see Fig 29) wherein a via conductor has an aspect ratio in a range of 0.5 to 1.0 ([0386-0388]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the substrate as taught by Nishioka in view of Yamazaki, wherein the via conductor has an aspect ratio in a range of 0.5 to 1.0as taught by En, in order to prevent a hole too large to fill with material, minimize failure of filling material, prevent metal ion diffusion difficulty, and prevent insulation from being too thin (En, [0386-0388]).
Regarding Claim 8, Nishioka in view of Yamazaki and En teaches the limitations of the preceding claim and Nishioka further teaches the wiring substrate (Fig 1) according to claim 3, wherein the first conductor layer (58B) has a thickness in a range of 7 μm to 20 μm ([0035,0040]; thickness of 58A or 58B is 15 μm to 20 μm).
Regarding Claim 9, Nishioka in view of Yamazaki and En teaches the limitations of the preceding claim and Nishioka further teaches the wiring substrate (Fig 1) according to claim 3, wherein the seed layer includes a (sputtering) film (52).
Claim states a “sputtering film” but “sputtering” does not represent product structure but only refers to the process by which the film is formed. Thus the claim is a product claim that recites a process step(s) of sputtering and is thus treated as a product-by-process claim. See MPEP 2113.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896