DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments/amendments, see Remarks/Claims, filed 07 January 2026, with respect to the rejection(s) of the claim(s) in the previous Office action have been fully considered and the responses set forth below.
Claim interpretation: Applicant has amended the claims to remove the “configured to” verbiage which previously invoked 112(f). The previous 112(f) has been withdrawn.
Claim Objection: Applicant has amended claim 1 to resolve the previously made objection. The objection to claim 11 made in the previous Office action has therefore been withdrawn.
35 USC §112(b) rejections: Applicant has amended the claims to recite “each of the NMOS transistor and to the PMOS transistor” and “a first semiconductor film” and “a second semiconductor film” to sufficiently clarify the scope of the claims. The 35 USC §112(b) rejections of the previous Office action have therefore been withdrawn.
Prior Art Rejections: Applicant submits that the “power supply configured to: generate voltages … to selectively provide a neutral back bias condition, a forward back bias condition, and a reverse back bias condition to each of the NMOS transistor and to the PMOS transistor” is intended to be interpreted with limitations from the specification to require the structural components of “selectively provide all three bias conditions … to each of {now amended} the NMOS and PMOS transistors independently” and “with independent voltage generation and control capabilities for each well type” (Remarks p. 11-12).
It is noted that these features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Applicant submits that ”the limitation recited above describes the result of the formation step (i.e., a power supply circuit having the structural capability to independently provide all three bias conditions to each transistor type).” (Remarks; p. 13). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). No such structural limitations are/were provided in the “formation step” of the rejected claims. Furthermore, the claims do not recite or require “a power supply capable of selectively and independently providing the three bias conditions to each transistor type”. Therefore, the prior rejections are proper.
Applicant has amended the claim to include “each of the NMOS transistor and PMOS transistor”, which is more specific than previously claimed, but does not include the recitation of “selectively and independently capable of providing … the three bias types...” It is noted that Applicant has provided (Remarks; 07 January 2026) the intention of the claims to be interpreted by these limitations from the specification. Furthermore, the claims do not recite any additional structural limitations that patently differentiate the claimed structure from the prior art. As such, and as required by the amendment, a new grounds of rejection is made below in light of Matsuura in view of newly discovered reference Vivek De et al. (US 6593799 B2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10-12, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Daisuke Matsuura et al. (US 20200007124 A1; hereinafter Matsuura) in view of Vivek De et al. (US 6593799 B2; hereinafter De; wherein portions of the specification are referred to in column:line format, i.e. C1:L1--L5 is column 1 line 1 to line 5).
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Regarding Claim 1, Matsuura teaches a semiconductor device (Fig. 1) of a silicon on insulator type (¶0001) including:
a NMOS transistor (Fig. 1; NMOS Transistor 18) in and on a first semiconductor film (Fig. 1; 26, 27, 28; ¶0030) separated from a P-type doped well (Fig. 1; P-Well 14; ¶0026) arranged in a carrier substrate (Fig. 1; 11; ¶0026) by a buried dielectric layer (Fig. 1; buried oxide film 16; ¶0027),
a PMOS transistor (Fig. 1; PMOS Transistor 17) in and on a second semiconductor film (Fig. 1; 21, 22, 23; ¶0029) separated from an N-type doped well (Fig. 1; N-Well 13; ¶0026) arranged in the carrier substrate (11) by the buried dielectric layer (16), and
a power supply circuit (Fig. 8; 52; ¶0074) configured to:
generate voltages (Fig. 1 and Fig. 8; VBp and VBn) in the P-type doped well (14) and the N-type doped well (13) (as shown in Fig. 1; ¶0082), and
generate a first non-zero negative voltage in the P-type doped well (14; ¶0034) and a first non-zero positive voltage in the N-type doped well (13; ¶0034),
wherein the NMOS (18) and PMOS (17) transistors have voltages (this limitation is satisfied by meeting the structural limitations of the claim and in view of ¶0034 where VBp, which is applied to the n-well 13 by the power supply circuit 52, is set to a positive voltage while VBn, which is applied to the p-well 14 by the power supply circuit 52, is a negative voltage).
Matsuura does not expressly disclose the power supply circuit (52) is configured to selectively provide a neutral back bias condition (with a first non-zero negative voltage in the P-type doped well and a first non-zero positive voltage in the N-type doped well), a forward back bias condition and a reverse back bias condition to each of the NMOS transistor (18) and to the PMOS transistor (17), wherein the NMOS (18) and PMOS (17) transistors have nominal threshold voltages in the neutral back bias condition.
Although Matsuura is silent regarding the specific voltage configurations, in the same field of endeavor, De (in reference to the entire disclosure) teaches CMOS devices (C14:L29--L65) provided with an on-die or off-die (C7:L35--L55) power supply circuit (C8:L59--L62) capable of being configured to selectively and independently provide neutral (zero), forward, and reverse body biasing to any/all PMOS or NMOS transistors, or both, in any static/quasi-static/dynamic/differential MOS logic and/or memory circuitry wherein the transistors may have nominal threshold voltages in the “zero” or “neutral” bias (C12:L8--L32; C8:L29--C9:L10; C3:L43--L59) by providing various bias voltages.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the physical transistor structures of Matsuura paired with the voltage generator/circuity/voltage configurations/bias of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 2, modified Matsuura teaches the device according to claim 1, wherein the power supply circuit (52) is configured to generate, for the forward back bias condition, a voltage which is higher than the first non-zero negative voltage in the P-type doped well (14) and a voltage which is lower than the first non-zero positive voltage in the N-type doped well (13) (52 generates voltages, this limitation is drawn toward the manner of operation of the device, and without any additional structural limitations, this is implicitly satisfied by the structure of modified Matsuura. MPEP 2114).
Alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configurations of the disclosure of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 3, modified Matsuura teaches the device according to claim 1, wherein the power supply circuit (52) is configured to generate, for the reverse back bias condition, a voltage which is lower than the first non-zero negative voltage in the P-type doped well (14) and a voltage which is higher than the first non-zero positive voltage in the N-type doped well (13) (52 generates voltages, this limitation is drawn toward the manner of operation of the device, and without any additional structural limitations, this is implicitly satisfied by the structure of modified Matsuura. MPEP 2114).
Alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configurations of the disclosure of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 8, modified Matsuura teaches the device according to claim 1, wherein the NMOS (18) and PMOS (17) transistors include a respective channel region (28, 23 respectively) including a concentration of doping species (doped respectively, ¶0030, ¶0029) to modulate a work function of the respective channel region so as to obtain the nominal threshold voltages in the neutral back bias condition (without any additional structural limitations, this is implicitly satisfied by the structure of modified Matsuura with the applied voltages of claim 1. MPEP 2114).
Regarding Claim 10, Matsuura teaches a method for manufacturing a semiconductor device (Fig. 1) of a silicon on insulator type (¶0001), the method comprising:
forming a NMOS transistor (Fig. 1; NMOS Transistor 18 is formed) in and on a first semiconductor film (Fig. 1; 26, 27, 28; ¶0030) separated from a P-type doped well arranged in a carrier substrate (Fig. 1; 11; ¶0026) by a buried dielectric layer (Fig. 1; buried oxide film 16; ¶0027);
forming a PMOS transistor (Fig. 1; PMOS Transistor 17 is formed) in and on a second semiconductor film (Fig. 1; 21, 22, 23; ¶0029) separated from an N-type doped well (Fig. 1; N-Well 13; ¶0026) arranged in the carrier substrate (11) by the buried dielectric layer (16); and
forming a power supply circuit (Fig. 8; 52 is formed; ¶0074) capable of generating voltages (Fig. 1 and Fig. 8; VBp and VBn) in the P-type doped well (14) and the N-type doped well (13), wherein the power supply circuit (52) is capable of applying a first non-zero negative voltage to the P-type doped well (14) and a first non-zero positive voltage to the N-type doped well (13) (¶0034),
wherein the NMOS and PMOS transistors have voltages (this limitation is satisfied by meeting the structural limitations of the claim, and in view of ¶0034 where VBp, which is applied to the n-well 13 by the power supply circuit 52, is set to a positive voltage while VBn, which is applied to the p-well 14 by the power supply circuit 52, is a negative voltage).
Matsuura does not expressly disclose wherein the power supply circuit (52) capable of selectively providing a neutral back bias condition, a forward back bias condition and a reverse back bias condition to each of the NMOS transistor (18) and to the PMOS transistor (17), wherein the power supply circuit (52) causes the neutral back bias condition by applying a first non-zero negative voltage to the P-type doped well (14) and a first non-zero positive voltage to the N-type doped well (13),
wherein the NMOS and PMOS transistors have nominal threshold voltages in the neutral back bias condition
Although Matsuura is silent regarding the specific voltage configurations, in the same field of endeavor, De (in reference to the entire disclosure) teaches CMOS devices (C14:L29--L65) provided with an on-die or off-die (C7:L35--L55) power supply circuit (C8:L59--L62) capable of being configured to selectively and independently provide neutral (zero), forward, and reverse body biasing to any/all PMOS or NMOS transistors, or both, in any static/quasi-static/dynamic/differential MOS logic and/or memory circuitry wherein the transistors may have nominal threshold voltages in the “zero” or “neutral” bias (C12:L8--L32; C8:L29--C9:L10; C3:L43--L59) by providing various bias voltages.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the physical transistor structures/formation of Matsuura paired with the voltage generator/circuity/voltage configurations/bias of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 11, modified Matsuura teaches the method according to claim 10, wherein the power supply circuit (52) causes the forward back bias condition by applying a voltage which is higher than the first non-zero negative voltage to the P-type doped well (14) and a voltage which is lower than the first non-zero positive voltage to the N-type doped well (13) (52 generates voltages, this limitation is drawn toward the manner of operation of the device, and without any additional structural or manufacturing limitations, this is implicitly satisfied by the structure, capability, and formation of the power supply of modified Matsuura. MPEP 2114).
Alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configurations of the disclosure of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 12, modified Matsuura teaches the method according to claim 10, wherein the power supply circuit (52) causes the reverse back bias condition by applying a voltage which is lower than the first non-zero negative voltage to the P-type doped well (14) and a voltage which is higher than the first non-zero positive voltage applied to the N-type doped well (13) (52 generates voltages, this limitation is drawn toward the manner of operation of the device, and without any additional structural or manufacturing limitations, this is implicitly satisfied by the structure, capability, and formation of the power supply of modified Matsuura. MPEP 2114).
Alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configurations of the disclosure of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 17, modified Matsuura teaches the method according to claim 10, wherein forming the NMOS (18) and PMOS (17) transistors includes forming a respective channel region (28, 23 respectively) including a concentration of doping species (doped respectively, ¶0030, ¶0029) to modulate a work function of the respective channel region to obtain the nominal threshold voltages in the neutral back bias condition (without any additional structural limitations or formation limitations, this is implicitly satisfied by the structure of modified Matsuura with the applied voltages of claim 10. MPEP 2114).
Regarding Claim 19, Matsuura teaches a semiconductor device (Fig. 1) of a silicon on insulator type (¶0001) including:
a NMOS transistor (Fig. 1; NMOS Transistor 18) in and on a first semiconductor film (Fig. 1; 26, 27, 28; ¶0030) separated from a P-type doped well (Fig. 1; P-Well 14; ¶0026) arranged in a carrier substrate (Fig. 1; 11; ¶0026) by a buried dielectric layer (Fig. 1; buried oxide film 16; ¶0027); and
a PMOS transistor (Fig. 1; PMOS Transistor 17) in and on a second semiconductor film (Fig. 1; 21, 22, 23; ¶0029) separated from an N-type doped well (Fig. 1; N-Well 13; ¶0026) arranged in the carrier substrate (11) by the buried dielectric layer (16).
Matsuura is silent regarding specifically wherein the NMOS transistor (18) and the PMOS transistor (17) being in a neutral back bias condition in response to a first non-zero negative voltage being applied to the P-type doped well and a first non-zero positive voltage being applied to the N-type doped well, and
wherein the NMOS and PMOS transistors have nominal threshold voltages in the neutral back bias condition (although the structure is capable in view of ¶0034 where VBp, which is applied to the n-well 13, is set to a positive voltage while VBn, which is applied to the p-well 14, is a negative voltage).
Although Matsuura is silent regarding the specific voltage configurations, in the same field of endeavor, De (in reference to the entire disclosure) teaches CMOS devices (C14:L29--L65) provided with an on-die or off-die (C7:L35--L55) power supply circuit (C8:L59--L62) capable of being configured to selectively and independently provide neutral (zero), forward, and reverse body biasing to any/all PMOS or NMOS transistors, or both, in any static/quasi-static/dynamic/differential MOS logic and/or memory circuitry wherein the transistors may have nominal threshold voltages in the “zero” or “neutral” bias (C12:L8--L32; C8:L29--C9:L10; C3:L43--L59) by providing various bias voltages.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the physical transistor structures of Matsuura paired with the voltage generator/circuity/voltage configurations/bias of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Regarding Claim 20, modified Matsuura teaches the device of claim 19, but is silent regarding wherein: the NMOS transistor (18) and the PMOS transistor (17) being in a forward back bias condition in response to a voltage higher than the first non-zero negative voltage being applied to the P-type doped well and a voltage lower than the first non-zero positive voltage being applied to the N-type doped well; and
the NMOS transistor and the PMOS transistor being in a reverse back bias condition in response to a voltage which is lower than the first non-zero negative voltage being applied to the P-type doped well and a voltage higher than the first non-zero positive voltage being applied to the N-type well (52 generates voltages, these limitations are drawn toward the manner of operation of the device, and without any additional structural or manufacturing limitations, this is implicitly satisfied by the structure, capability, and formation of the power supply of modified Matsuura. MPEP 2114).
Alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configurations of the disclosure of De to arrive at the claimed limitations in order to provide varying degrees of leakage and drive currents to an assortment of n- and p-MOSFETs on the same die (C8:L63—C9:L10).
Claims 4-5, 9, 13-14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Daisuke Matsuura et al. (US 20200007124 A1; hereinafter Matsuura) in view of Vivek De et al. (US 6593799 B2; hereinafter De) and Francois Andrieu (US 20180026036 A1; hereinafter Andrieu).
Regarding Claim 4, modified Matsuura teaches the device according to claim 1, wherein the NMOS transistor (18) includes a tensile strained channel region (28 is the channel region of the NMOS and is p-type doped; ¶0030), in the respective semiconductor film, and the PMOS transistor (17) includes a compressively strained channel region (23 is the channel region of the PMOS and is n-type doped; ¶0029), in the respective semiconductor film.
Matsuura is silent regarding wherein the p-type doped channel (28) of the NMOS transistor (18) is tensile strained, and the n-type doped channel (23) of the PMOS transistor (17) is compressively strained.
In the same field of endeavor, Andrieu teaches a similar NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein NMOS transistors (11 to 14; ¶0024) that have a p-type doped channel region (¶0031) and PMOS transistors (21 to 24; ¶0027) that have a n-type doped channel region (¶0032), wherein the channel of the NMOS transistor is tensile strained (¶0034) and the channel of the PMOS transistor is compressively strained (¶0034).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the tensile strained NMOS transistor channel region and compressive strained PMOS transistor channel region of Andrieu in the device of Matsuura. One of ordinary skill in the art would recognize that utilizing the features of Andrieu in Matsuura improves the mobility of electrons and reduces the threshold voltage of the NMOS transistors while improving the mobility of holes and reducing the threshold voltage of the PMOS transistors (Andrieu; ¶0034).
Regarding Claim 5, modified Matsuura teaches the device according to claim 1, wherein the PMOS transistor (17) includes a channel region (23).
Matsuura is silent regarding the material of the channel region, wherein it is made of silicon-germanium alloy, in the respective semiconductor film, with a germanium concentration greater than 25% atomic percent.
In the same field of endeavor, Andrieu teaches a similar NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein a PMOS transistor (any of 21 to 24; ¶0027) has a composition of SiGe with 25-35% germanium, and a reduction of the threshold voltage of the PMOS transistor is dependent on the percentage of germanium (Andrieu; ¶0082).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have SiGe in the PMOS channel (of Andrieu) with a Ge percentage above 25% in the device of Matsuura in order to optimize the result effective variable of threshold voltage of the transistor. MPEP 2144.05 II.
Regarding Claim 9, modified Matsuura teaches the device according to claim 1, including at least one CMOS circuit (Fig. 1; semiconductor device 10) provided with the NMOS transistor (18) and the PMOS transistor (17), which are configured to have nominal threshold voltages in the neutral back bias condition (see claim 1). Modified Matsuura is silent regarding the threshold voltages in at least one of the following intervals:
an interval of super low threshold voltages comprised between 0.15 V and 0.25 V in absolute values;
an interval of low threshold voltages between 0.2 V and 0.3 V in absolute values;
an interval of lower median threshold voltages between 0.25 V and 0.35 V in absolute values;
an interval of upper median threshold voltages between 0.3 V and 0.4 V in absolute values; or
an interval of high threshold voltages (HVT) between 0.35 V and 0.45 V in absolute values.
However, Matsuura discloses in ¶0034 (also in view of the disclosure of De) that the threshold voltages of the transistors are controlled by the applied substrate bias. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the threshold voltages of the transistors by adjusting the substrate bias (Matsuura; ¶0034). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Furthermore, in the same field of endeavor, Andrieu teaches a similar device with a complimentary NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein NMOS transistors (11 to 14; ¶0024) and PMOS transistors (21 to 24; ¶0027) can be variously configured to have threshold voltages (¶0030-¶0032, ¶0069) in the claimed voltage ranges (¶0003). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the threshold voltage ranges of Matsuura to be within the claimed range, in the manner of Andrieu (¶0003, ¶0030-¶0032, ¶0097-¶0098) in order to provide a device with fast access logic gates and low power consumption logic gates in the same integrated circuit (Andrieu; ¶0002).
Regarding Claim 13, modified Matsuura teaches the method according to claim 10, wherein: forming the NMOS transistor (18) comprises forming a tensile strained channel region (28 is the channel region of the NMOS and is p-type doped; ¶0030) in the respective semiconductor film; and forming the PMOS transistor (17) includes forming a compressively strained channel region (23 is the channel region of the PMOS and is n-type doped; ¶0029) in the respective semiconductor film.
Matsuura is silent regarding wherein the p-type doped channel (28) of the NMOS transistor (18) is tensile strained, and the n-type doped channel (23) of the PMOS transistor (17) is compressively strained.
In the same field of endeavor, Andrieu teaches a similar NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein NMOS transistors (11 to 14; ¶0024) that have a p-type doped channel region (¶0031) and PMOS transistors (21 to 24; ¶0027) that have a n-type doped channel region (¶0032), wherein the channel of the NMOS transistor is tensile strained (¶0034) and the channel of the PMOS transistor is compressively strained (¶0034).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the tensile strained NMOS transistor channel region and compressive strained PMOS transistor channel region of Andrieu in the device of Matsuura. One of ordinary skill in the art would recognize that utilizing the features of Andrieu in Matsuura improves the mobility of electrons and reduces the threshold voltage of the NMOS transistors while improving the mobility of holes and reducing the threshold voltage of the PMOS transistors (Andrieu; ¶0034).
Regarding Claim 14, modified Matsuura teaches the method according to claim 10, wherein forming the PMOS transistor (17) includes forming a channel region (23).
Matsuura is silent regarding the material of the channel region, wherein it is made of silicon-germanium alloy in the respective semiconductor film, with a germanium concentration greater than 25% atomic percent.
In the same field of endeavor, Andrieu teaches a similar NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein a PMOS transistor (any of 21 to 24; ¶0027) has a composition of SiGe with 25-35% germanium, and a reduction of the threshold voltage of the PMOS transistor is dependent on the percentage of germanium (Andrieu; ¶0082).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have SiGe in the PMOS channel (of Andrieu) with a Ge percentage above 25% in the device of Matsuura in order to optimize the result effective variable of threshold voltage of the transistor. MPEP 2144.05 II.
Regarding Claim 18, modified Matsuura teaches the method according to claim 10, further comprising forming at least one CMOS circuit (Fig. 1; semiconductor device 10) provided with the NMOS transistor (18) and the PMOS transistor (17), the method further comprising providing, by the at least one CMOS circuit, the NMOS and PMOS transistors with nominal threshold voltages in the neutral back bias condition (see claim 10). Matsuura is silent regarding the threshold voltages being in at least one of the following intervals:
an interval of super low threshold voltages between 0.15 V and 0.25 V in absolute values;
an interval of low threshold voltages comprised 0.2 V and 0.3 V in absolute values;
an interval of lower median threshold voltages between 0.25 V and 0.35 V in absolute values;
an interval of upper median threshold voltages between 0.3 V and 0.4 V in absolute values; or
an interval of threshold voltages between 0.35 V and 0.45 V in absolute values.
However, Matsuura discloses in ¶0034 (also in view of the disclosure of De) that the threshold voltages of the transistors are controlled by the applied substrate bias. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the threshold voltages of the transistors by adjusting the substrate bias (Matsuura; ¶0034). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Furthermore, in the same field of endeavor, Andrieu teaches a similar device with a complimentary NMOS and PMOS transistor configuration (Andrieu; Fig. 1) wherein NMOS transistors (11 to 14; ¶0024) and PMOS transistors (21 to 24; ¶0027) can be variously configured to have threshold voltages (¶0030-¶0032, ¶0069) in the claimed voltages ranges (¶0003). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the threshold voltage ranges of Matsuura to be within the claimed range, in the manner of Andrieu (¶0003, ¶0030-¶0032, ¶0097-¶0098) in order to provide a device with fast access logic gates and low power consumption logic gates in the same integrated circuit (Andrieu; ¶0002).
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Daisuke Matsuura et al. (US 20200007124 A1; hereinafter Matsuura) in view of Vivek De et al. (US 6593799 B2; hereinafter De) and Guillaume Ribes et al. (US 20180090389 A1; hereinafter Ribes).
Regarding Claim 6, modified Matsuura teaches the device according to claim 1, wherein the NMOS (18) and PMOS (17) transistors include a gate dielectric layer (29 and 24 respectively; ¶0030 and ¶0029) located between, respectively, a gate conductive region (30 and 25, respectively; ¶0030 and ¶0029) and the semiconductor film (26, 27, 28 and 21, 22, 23, respectively) (as shown in Fig. 1).
Matsuura is silent regarding the material of the gate dielectric layer, wherein the gate dielectric layer is comprising nitrogen to form a silicon oxynitride SiON layer.
In the same field of endeavor, Ribes teaches a similar device with NMOS and PMOS transistors (Ribes; Fig. 1) wherein a gate dielectric layer (11; ¶0027) comprises nitrogen and is SiON (Ribes; ¶0031).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiON dielectric layer of Ribes in the device of Matsuura because the substitution of a known equivalent (gate dielectric) for another known equivalent (for the same purpose as a gate dielectric) is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Furthermore, Ribes states in ¶0027 that the configuration contributes to the lowering of threshold voltages in the transistor.
Regarding Claim 7, modified Matsuura teaches the device according to claim 1, wherein the NMOS (18) and PMOS (17) transistors include a gate conductive region (30 and 25, respectively; ¶0030 and ¶0029).
Matsuura is silent regarding the material of the gate conductive regions including titanium nitride and a titanium nitride additive selected from lanthanum and aluminum, to modulate a work function of a gate of the NMOS transistor and a gate of the PMOS transistor to obtain the nominal threshold voltages in the neutral back bias condition.
In the same field of endeavor, Ribes teaches a similar device with NMOS and PMOS transistors (Ribes; Fig. 1) wherein gate conductive regions (15, 17, 19, 21; ¶0024) include titanium nitride and an additive lanthanum (Ribes; ¶0024) which leads to an optimization of the threshold voltage (Ribes; ¶0028).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the configuration of the gate conductive regions of Ribes in the device of Matsuura in order to optimize the threshold voltages of the transistors (Ribes; ¶0028). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding Claim 15, modified Matsuura teaches the method according to claim 10, wherein forming the NMOS (18) and PMOS (17) transistors include forming a gate dielectric layer (29 and 24 respectively; ¶0030 and ¶0029) located between, respectively, a gate conductive region (30 and 25, respectively; ¶0030 and ¶0029) and the semiconductor film (26, 27, 28 and 21, 22, 23, respectively) (as shown in Fig. 1).
Matsuura is silent regarding the material of the gate dielectric layer, wherein the gate dielectric layer comprises nitrogen so as to form a silicon oxynitride SiON layer.
In the same field of endeavor, Ribes teaches a similar device with NMOS and PMOS transistors (Ribes; Fig. 1) wherein a gate dielectric layer (11; ¶0027) comprises nitrogen and is SiON (Ribes; ¶0031).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiON dielectric layer of Ribes in the device of Matsuura because the substitution of a known equivalent (gate dielectric) for another known equivalent (for the same purpose as a gate dielectric) is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Furthermore, Ribes states in ¶0027 that the configuration contributes to the lowering of threshold voltages in the transistor.
Regarding Claim 16, modified Matsuura teaches the method according to claim 10, wherein forming the NMOS (18) and PMOS (17) transistors include a gate conductive region (30 and 25, respectively; ¶0030 and ¶0029).
Matsuura is silent regarding the material of the gate conductive regions including titanium nitride and a titanium nitride additive selected from lanthanum and aluminum, so as to modulate a work function of a gate of the NMOS transistor and a gate of the PMOS transistor to obtain the nominal threshold voltages in the neutral back bias condition.
In the same field of endeavor, Ribes teaches a similar device with NMOS and PMOS transistors (Ribes; Fig. 1) wherein gate conductive regions (15, 17, 19, 21; ¶0024) include titanium nitride and an additive lanthanum (Ribes; ¶0024) which leads to an optimization of the threshold voltage (Ribes; ¶0028).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the configuration of the gate conductive regions of Ribes in the device of Matsuura in order to optimize the threshold voltages of the transistors (Ribes; ¶0028). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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