Prosecution Insights
Last updated: July 17, 2026
Application No. 18/324,612

Package Redistribution Layer Structures for Stress Mitigation and Alignment Tolerance

Final Rejection §102§103
Filed
May 26, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
2 (Final)
92%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1688
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 18 is is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US pub 20200381382). With respect to claim 18, Chiu et al. teach an electronic system comprising (see figs. 1-9, particularly fig. 1N and associated text): a module substrate DT2; an electronic package 400 mounted on the module substrate, wherein the electronic package comprises: an electronic component 110,110a including a contact terminal 150; a package redistribution layer (RDL) RDL on the electronic component, wherein the package RDL comprises: a plurality of wiring layers P1, P2; and a via line V1a that connects a first wiring layer of the plurality of wiring layers to the contact terminal of the electronic component, or to another wiring layer of the plurality of wiring layers. Claim(s) 19, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US pub 20200381382). With respect to claim 19, Chiu et al. teach the package RDL comprises a plurality of dielectric layers 220, 240, 260 but fail to teach the dielectric layers having an elastic modulus below 20 GPa. However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the elastic modulus for the dielectric layers through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that the claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05. With respect to claim 20, Chiu et al. teach the package RDL comprises a plurality of package terminals 304, wherein the plurality of package terminals is bonded to the module substrate with a plurality of solder bumps 304. See fig. 1N and associated text. With respect to claim 21, Chiu et al. teach the via line is characterized by a line width (lateral length) and a longitudinal line length (vertical length) that is greater than the line width. See fig. 1N and associated text. Allowable Subject Matter Claims 1-9 and 10-17 are allowed. Response to Arguments Applicant's arguments filed 5/5/26 have been fully considered but they are not persuasive. See the above rejections. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 26, 2023
Application Filed
Mar 03, 2025
Response after Non-Final Action
Feb 23, 2026
Non-Final Rejection mailed — §102, §103
May 05, 2026
Response Filed
Jul 09, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685219
PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN AN INTEGRATED DEVICE AND A METALLIZATION PORTION
3y 10m to grant Granted Jul 14, 2026
Patent 12685214
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 7m to grant Granted Jul 14, 2026
Patent 12685213
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
3y 2m to grant Granted Jul 14, 2026
Patent 12685233
THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS
2y 0m to grant Granted Jul 14, 2026
Patent 12677686
Electronic Package with Components Mounted at Two Sides of a Layer Stack
3y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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