DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8, 10-16, and 18-21 in the reply filed on 11/20/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US pub 20200381382).
With respect to claim 1, Chiu et al. teach an electronic package structure comprising (see figs. 1-9, particularly fig. 1N and associated text):
an electronic component 110,110a including a contact terminal 150;
a package redistribution layer (RDL) RDL on the electronic component, wherein the package RDL comprises:
a plurality of wiring layers P1,P2; and
a via line V1a that connects a first wiring layer of the plurality of wiring layers to the contact terminal of the electronic component or to another wiring layer of the plurality of wiring layers.
With respect to claim 2, Chiu et al. teach the via line is characterized by a line width (lateral width) and a longitudinal line length (vertical length) that is greater than the line width. See fig. 1N and associated text.
With respect to claim 3, Chiu et al. teach the via line connection is fully supported by the first wiring layer such that an entire shadow of the line via connection is directly above a wiring trace of the first wiring layer. See fig. 1N and associated text.
With respect to claim 4, Chiu et al. teach the contact terminal has a minimum width (lateral width) that is greater than the line width of the via line. See fig. 1N and associated text.
With respect to claim 8, Chiu et al. teach the electronic component comprises a second contact terminal (right or left of 150), and the via line is in direct contact with the second contact terminal. See fig. 1N and associated text.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13, 14, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US pub 20200381382).
With respect to claim 13, Chiu et al. teach the package RDL comprises a plurality of dielectric layers 220, 240, 260 but fail to teach the dielectric layers having an elastic modulus below 20 GPa.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the elastic modulus for the dielectric layers through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that the claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 14, Chiu et al. fail to teach the plurality of dielectric layer is a plurality of polymer layers.
However, the use of the dielectric layer made of polymer layers is well-known in semiconductor art.
With respect to claim 15, Chiu et al. teach at least one of the plurality of wiring layers includes a wiring bridge P1 that is electrically connected with the via line. See fig. 1N and associated text.
With respect to claim 16, Chiu et al. fail to teach connecting a power or supply to the wiring bridge or metal trace.
However, the connection of a power or supply to wiring bridge or metal trace is well-known in semiconductor art.
Claim(s) 18 is is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US pub 20200381382).
With respect to claim 18, Chiu et al. teach an electronic system comprising (see figs. 1-9, particularly fig. 1N and associated text):
a module substrate DT2;
an electronic package 400 mounted on the module substrate, wherein the electronic package comprises:
an electronic component 110,110a including a contact terminal 150;
a package redistribution layer (RDL) RDL on the electronic component, wherein the package RDL comprises:
a plurality of wiring layers P1, P2; and
a via line V1a that connects a first wiring layer of the plurality of wiring layers to the contact terminal of the electronic component, or to another wiring layer of the plurality of wiring layers.
Claim(s) 19, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US pub 20200381382).
With respect to claim 19, Chiu et al. teach the package RDL comprises a plurality of dielectric layers 220, 240, 260 but fail to teach the dielectric layers having an elastic modulus below 20 GPa.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the elastic modulus for the dielectric layers through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that the claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 20, Chiu et al. teach the package RDL comprises a plurality of package terminals 304, wherein the plurality of package terminals is bonded to the module substrate with a plurality of solder bumps 304. See fig. 1N and associated text.
With respect to claim 21, Chiu et al. teach the via line is characterized by a line width (lateral length) and a longitudinal line length (vertical length) that is greater than the line width. See fig. 1N and associated text.
Allowable Subject Matter
Claims 5-7 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having a via of a RDL contacting a terminal and wirings and having a lateral length greater than a lateral width as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897