DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa (US Patent No. 5,471,366 A).
Regarding claim 16, Ozawa teaches a method comprising:
depositing a first heat spreader (col. 6 lines 44-45: 33-1) on a first integrated circuit die (33-1 deposited on chip 32-1) of an integrated circuit package (figs. 3 & fig. 5A among others: 33-1 and 33-2 comprised by integrated circuit package 30);
depositing a second heat spreader (col. 6 lines 44-45: 33-2) on a second integrated circuit die of the integrated circuit package (fig. 5B: 33-2 deposited on die 32-2);
depositing a dielectric mold material (col. 7 lines 3-4: resin package body 34) to encompass the first integrated circuit die and the second integrated circuit die on the integrated circuit package (fig. 5C: resin body deposited to encompass 32-1 and 32-2);
removing material from a top surface of the integrated circuit package to expose the first heat spreader and the second heat spreader at the top surface of the integrated circuit package (col. 7 lines 4-6 & fig. 5D: surface of 34 polished to expose 33-1 and 33-2); and
depositing a thermally conductive material (col. 5 line 27: silicone adhesive, which is a type of thermal interface material) on the top surface of the integrated circuit package (figs. 3: 46 deposited on top surface of 30).
Regarding claim 17, Ozawa teaches the method of claim 16, wherein the thermally conductive material is deposited conformally on the integrated circuit package (fig. 3: 46 deposited conformally on top surface of 30).
Regarding claim 20, Ozawa teaches the method of claim 16, further comprising attaching a heat sink (col. 4 lines 51-52: heat sink block 36) to the top surface of the integrated circuit package (figs, 3, 5F: 36 attached to top surface of 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong (PG Pub. No. US 2008/0067645 A1).
Regarding claim 1, Ozawa teaches an integrated circuit package (col. 8 line 38 & fig. 11: 120) comprising:
a package substrate (col. 8 line 44: 121a);
a first integrated circuit die (col. 8 line 48: 81-2) electrically coupled to the package substrate via wire bond connectors (fig. 11 & col. 8 line 54: 81-2 coupled to 121a through unlabeled bonding wires, equivalent to 32x of figs. 7-8);
a second integrated circuit die (col. 8 line 48: 32-1) coupled to the package substrate (fig. 11: 32-1 at least indirectly coupled to 121a);
a heat spreader (col. 8 line 64: thermally conductive block 82-2) coupled to the first integrated circuit die (col. 8 lines 62-64: at least one heat path includes 81-2 and 82-2, such that 82-2 is at least thermally coupled to 81-2); and
a dielectric material (unlabeled resin body, equivalent to 34 of figs. 7-8) encompassing the first integrated circuit die and the second integrated circuit die on the package substrate (fig. 11: resin body encompasses 81-2 and 32-1), wherein a top surface of the heat spreader is aligned with a top surface of the dielectric material (fig. 11: top surface of 82-2 aligned w/ top surface of resin body).
Ozawa further teaches alternative embodiments (fig. 3 among others) including a heat spreader (33-2) coupled to a first integrated circuit die (32-1) via a thermal interface material (TIM) (fig. 3 & col. 5 lines 3-5: 33-2 coupled to 32-1 via thermal adhesive 42).
Ozawa does not explicitly teach the embodiment of fig. 11 further includes a thermal interface material (TIM) coupling the heat spreader (82-2) to the first integrated circuit die (81-2).
Foong teaches an integrated circuit package (¶ 0018 & fig. 4: 100, similar to 120 of Ozawa) including a heat spreader (¶ 0014: 50, similar to 82-2 of Ozawa) coupled to a first integrated circuit die (¶ 0018: 104, similar to 81-2 of Ozawa) via a thermal interface material (TIM) (¶ 0021 & fig. 4: 50 coupled to 104 via thermal adhesive 114, similar to 42 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the package of Ozawa to further include a thermal interface material (TIM) coupling the heat spreader to the first integrated circuit die, as a means to facilitate heat transfer from the first integrated circuit die to the heat spreader (Foong, ¶ 0021), further improving the heat dissipation efficiency of Ozawa.
Regarding claim 4, Ozawa in view of Foong teaches the integrated circuit package of claim 1, wherein the heat spreader is a first heat spreader (Ozawa, 82-2 is a 1st heat spreader), the TIM is a first TIM (Foong, 114 is a first thermal adhesive), and the integrated circuit package further comprises a second heat spreader (Ozawa, col. 8 line 64: second thermally conductive block 33-1) coupled to the second integrated circuit die (Ozawa, fig. 11: 33-1 coupled to die 32-1).
Ozawa in view of Foong as applied to claim 1 above does not explicitly teach the second heat spreader (33-1) coupled to the second integrated circuit die (32-1) via a second TIM.
However, Ozawa teaches embodiments (fig. 3 among others) including a second heat spreader (33-2) coupled to a second integrated circuit die (32-2) via a second TIM (col. 5 lines 3-5 & fig. 3: 33-2 coupled to 32-3 via a second portion of thermally conductive material 42).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Ozawa in view of Foong to further comprise a second TIM between the second heat spreader and second integrated circuit die, as a means to ensure adhesion between the heat spreader and die, and minimize thermal resistance between the semiconductor chips and the corresponding thermally conductive blocks (Ozawa, col. 5 lines 60-62).
Regarding claim 5, Ozawa in view of Foong teaches the integrated circuit package of claim 4, wherein a top surface of the second heat spreader is aligned with the top surface of the dielectric material (Ozawa, fig. 11: top surface of 33-1 aligned with top surface of unlabeled resin body).
Regarding claim 6, Ozawa in view of Foong teaches the integrated circuit package of claim 4, wherein a width of the second heat spreader is less than or equal to a width of the second integrated circuit die (Ozawa, fig. 11: width of 33-1 substantially equal to width of 32-1).
Regarding claim 9, Ozawa in view of Foong teaches the integrated circuit package of claim 1, comprising dielectric material (Ozawa, unlabeled resin body).
Ozawa in view of Foong as applied to claim 1 above fails to teach the package further comprising a thermally conductive material on the top surface of the dielectric material.
However, Ozawa teaches an embodiment (figs. 3 & 12 among others) including a thermally conductive material (col. 5 lines 26-46: adhesive layer 46, which provides a portion of thermally conductive path 50) on a top surface of a dielectric material (col. 6 lines 14-19 & fig. 12: 46 disposed on top surface of resin body 34 and/or 131).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Ozawa in view of Foong with a thermally conductive material on the top surface of the dielectric material, as a means to effectively eliminate degradation of thermal resistance at the interface between the dielectric material (Ozawa, 34) and a head sink (Ozawa, 36), enhancing reliability of the package.
Regarding claim 10, Ozawa in view of Foong teaches the integrated circuit package of claim 9, wherein the thermally conductive material is conformal to an outer surface of the integrated circuit package (Ozawa, fig. 12: 46 conformal to upper surface of 131).
Claims 11 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Chan et al. (PG Pub. No. US 2004/0106230 A1) and Foong.
Regarding claim 11, Ozawa teaches a system comprising:
an integrated circuit package (fig. 11) comprising:
a package substrate (col. 8 line 44: 121a);
multiple integrated circuit dies (col. 8 line 48: 81-2 & 32-1) coupled to the package substrate (fig. 11: 81-2 & 32-1 coupled to 121a by unlabeled connectors & 121b), a first integrated circuit die electrically coupled to the package substrate via wire bond connectors (col. 8 lines 48-54 & fig. 11: 81-2 coupled to 121a by unlabeled bonding wires, equivalent to 32x of fig. 3) and a second integrated circuit die electrically coupled to the package substrate via electrical connections (col. 8 lines 43-50 & fig. 11: 32-1 electrically coupled to 121a by unlabeled connectors);
a heat spreader (col. 8 lines 64: thermally conductive block 82-2) coupled to the first integrated circuit die (col. 8 lines 62-64: 82-2 thermally coupled to 81-2); and
a dielectric material encompassing the integrated circuit dies on the package substrate (fig. 11: unlabeled resin body, equivalent to 34 of fig. 3, encompasses 81-2 & 32-1), wherein a top surface of the heat spreader is aligned with a top surface of the dielectric material (fig. 11: top surface of 82-2 aligned with top surface of unlabeled resin body).
Ozawa fails to teach the integrated circuit package of fig. 11 further comprising a circuit board, the unlabeled electrical connections include solder-based material, and the heat spreader (82-2) coupled to the first integrated circuit die (81-2) via a thermal interface material (TIM).
However, Ozawa teaches an embodiment (col. 4 lines 40-44 & figs. 2-3) including a circuit board (col. 5 line 39: 48) and an integrated circuit package (30) comprising a package substrate (col. 6 lines 38-39: 31, similar to 121a of fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the embodiment of fig. 11 to further include a circuit board, as a means to integrate the package into a system such as a computer (col. 5 lines 39-40), increasing functionality of the package.
Ozawa as modified above does not teach the unlabeled electrical connections include solder-based material, and the heat spreader (82-2) coupled to the first integrated circuit die (81-2) via a thermal interface material (TIM).
Chan teaches an integrated circuit package (fig. 6) including an integrated circuit die (¶ 0011: 120 and/or 130) coupled to a package substrate (¶ 0012: 140) via solder-based electrical connections (¶ 0015: 162).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the electrical connections of Ozawa with solder-based material, as a means to provide connections suitable for flip-chip connection in a single step (Chan, ¶ 0015).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the solder-based material of Chan is suitable to provide the electrical connections of Ozawa.
Ozawa in view of Chan does not teach the heat spreader (82-2) coupled to the first integrated circuit die (81-2) via a thermal interface material (TIM).
Foong teaches an integrated circuit package (¶ 0018 & fig. 4: 100, similar to 120 of Ozawa) including a heat spreader (¶ 0014: 50, similar to 82-2 of Ozawa) coupled to a first integrated circuit die (¶ 0018: 104, similar to 81-2 of Ozawa) via a thermal interface material (TIM) (¶ 0021 & fig. 4: 50 coupled to 104 via thermal adhesive 114, similar to 42 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the package of Ozawa to further include a thermal interface material (TIM) coupling the heat spreader to the first integrated circuit die, as a means to facilitate heat transfer from the first integrated circuit die to the heat spreader (Foong, ¶ 0021), further improving the heat dissipation efficiency of Ozawa.
Regarding claim 14, Ozawa in view of Chan and Foong teaches the system of claim 11, wherein the heat spreader is a first heat spreader (Ozawa, 82-2 is a first heat spreader), the TIM is a first TIM (Foong, 114 is a first TIM), and the integrated circuit package further comprises a second heat spreader a second heat spreader (Ozawa, col. 8 line 64: second thermally conductive block 33-1) coupled to the second integrated circuit die (Ozawa, fig. 11: 33-1 coupled to die 32-1), a top surface of the second heat spreader aligned with the top surface of the dielectric material (Ozawa, fig. 11: top surface of 33-1 aligned with top surface of unlabeled resin body).
Ozawa in view of Chan and Foong as applied to claim 1 above does not explicitly teach the second heat spreader (33-1) coupled to the second integrated circuit die (32-1) via a second TIM.
However, Ozawa teaches embodiments (fig. 3 among others) including a second heat spreader (33-2) coupled to a second integrated circuit die (32-2) via a second TIM (col. 5 lines 3-5 & fig. 3: 33-2 coupled to 32-3 via a second portion of thermally conductive material 42).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Ozawa in view of Chan and Foong to further comprise a second TIM between the second heat spreader and second integrated circuit die, as a means to ensure adhesion between the heat spreader and die, and minimize thermal resistance between the semiconductor chips and the corresponding thermally conductive blocks (Ozawa, col. 5 lines 60-62).
Regarding claim 15, Ozawa in view of Chan and Foong teaches the system of claim 11, further comprising dielectric material (Ozawa, unlabeled resin body).
Ozawa in view of Chan and Foong as applied to claim 1 above fails to teach the package further comprising a thermally conductive material on the top surface of the dielectric material.
However, Ozawa teaches an embodiment (figs. 3 & 12 among others) including a thermally conductive material (col. 5 lines 26-46: adhesive layer 46, which provides a portion of thermally conductive path 50) on a top surface of a dielectric material (col. 6 lines 14-19 & fig. 12: 46 disposed on top surface of resin body 34 and/or 131).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package of Ozawa in view of Chan and Foong with a thermally conductive material on the top surface of the dielectric material, as a means to effectively eliminate degradation of thermal resistance at the interface between the dielectric material (Ozawa, 34) and a head sink (Ozawa, 36), enhancing reliability of the package.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong as applied to claim 1 above, and further in view of Irie et al. (PG Pub. No. US 2003/0080412 A1).
Regarding claim 2, Ozawa in view of Foong teaches the integrated circuit package of claim 1, comprising wire bond connectors (Ozawa, fig. 11: unlabeled bonding wires, equivalent to 32x of fig. 7) and dielectric material (unlabled resin body, equivalent to 34 of fig. 7).
Ozawa in view of Foong fails to teach wherein at least a portion of the wire bond connectors have a portion thereof exposed at the top surface of the dielectric material.
Irie teaches an integrated circuit package (fig. 2B among others) including at least a portion of wire bond connectors (¶ 0057: 5a, 5b, similar to 32x of Ozawa) having a portion thereof exposed at a top surface of a dielectric material (fig. 2B: 5a/5b include portions 8a/8b exposed at a top surface of unlabeled resin body, similar to 34 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the wire bond connectors of Ozawa in view of Foong with portions exposed from the dielectric material, as a means to provide a circuit for monitoring connectivity between cooling device (Irie, ¶ 0022: 13 and/or Ozawa, 36) and the integrated circuit package, improving operation reliability of the package (Irie, ¶ 0042).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong as applied to claim 1 above, and further in view of Shibuya et al (PG Pub. No. US 2020/0194357 A1).
Regarding claim 3, Ozawa in view of Foong teaches the integrated circuit package of claim 1, comprising a second integrated circuit die (Ozawa, 32-1) and a top surface of dielectric material (Ozawa, top surface of resin body).
Ozawa in view of Foong does not teach wherein a top surface of the second integrated circuit die is aligned with the top surface of the dielectric material.
Shibuya teaches an integrated circuit package (¶ 0035: 300) including a top surface of a second integrated circuit die (¶ 0036: 320, similar to 32-1 of Ozawa) aligned with a top surface of a dielectric material (¶ 0041 & fig. 3D: top surface of 320 aligned with top surface of mold compound 302, equivalent to 34 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the top surface of the second circuit die of Ozawa in view of Foong to align with the top surface of the dielectric material, as a means to facilitate cooling by allowing direct contact between the die and a heat sink (Shibuya, ¶ 0042). Such a configuration would also reduce manufacturing cost by omitting the second heat spreader of Ozawa.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong as applied to claim 1 above, and further in view of Lin et al. (PG Pub. No. US 2020/0194444 A1).
Regarding claim 7, Ozawa in view of Foong teaches the integrated circuit package of claim 4, comprising a second heat spreader (Ozawa, 33-1) and a second integrated circuit die (Ozawa, 32-1).
Ozawa in view of Foong fails to teach wherein a width of the second heat spreader is greater than a width of the second integrated circuit die.
Lin teaches an integrated circuit package (fig. 4: 10) including a heat spreader (¶ 0051: 704, similar to 33-1 of Ozawa) and an integrated circuit die (¶ 0049: 701, similar to 32-1 of Ozawa), wherein a width of the heat spreader is greater than a width of the integrated circuit die (fig. 4: width of 704 greater than width of 701).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the integrated circuit Package of Ozawa in view of Foong to include a width of the second heat spreader is greater than a width of the second integrated circuit die, as a means to increase the heat capacity of the total assembly (Lin, ¶ 0051).
Furthermore, such a modification would have involved a mere change in the size of a component (increased width of 33-1 of Ozawa, and/or decreased width of 32-1 of Ozawa). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong as applied to claim 1 above, and further in view of Chan.
Regarding claim 8, Ozawa in view of Foong teaches the integrated circuit package of claim 1, wherein the second integrated circuit die is coupled to the package substrate via electrical connections (Ozawa, col. 8 lines 43-48 & fig. 11: 32-1 electrically coupled to 121a via unlabeled connectors).
Ozawa in view of Foong fails to teach the unlabeled electrical connections are solder-based.
Chan teaches an integrated circuit package (fig. 6) including an integrated circuit die (¶ 0011: 120 and/or 130) coupled to a package substrate (¶ 0012: 140) via solder-based electrical connections (¶ 0015: 162).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the electrical connections of Ozawa in view of Foong with solder-based material, as a means to provide connections suitable for flip-chip connection in a single step (Chan, ¶ 0015).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the solder-based material of Chan is suitable to provide the electrical connections of Ozawa in view of Foong.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong and Chan as applied to claim 11 above, and further in view of Irie.
Regarding claim 12, Ozawa in view of Foong and Chan teaches the system of claim 11, comprising wire bond connectors (Ozawa, fig. 11: unlabeled bonding wires, equivalent to 32x of fig. 7) and dielectric material (unlabled resin body, equivalent to 34 of fig. 7).
Ozawa in view of Foong and Chan fails to teach wherein at least a portion of the wire bond connectors have a portion thereof exposed at the top surface of the dielectric material.
Irie teaches an integrated circuit package (fig. 2B among others) including at least a portion of wire bond connectors (¶ 0057: 5a, 5b, similar to 32x of Ozawa) having a portion thereof exposed at a top surface of a dielectric material (fig. 2B: 5a/5b include portions 8a/8b exposed at a top surface of unlabeled resin body, similar to 34 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the wire bond connectors of Ozawa in view of Foong and Chan with portions exposed from the dielectric material, as a means to provide a circuit for monitoring connectivity between cooling device (Irie, ¶ 0022: 13 and/or Ozawa, 36) and the integrated circuit package, improving operation reliability of the package (Irie, ¶ 0042).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa in view of Foong and Chan as applied to claim 11 above, and further in view of Shibuya.
Regarding claim 13, Ozawa in view of Foong teaches the system of claim 11, comprising a second integrated circuit die (Ozawa, 32-1) and a top surface of dielectric material (Ozawa, top surface of resin body).
Ozawa in view of Foong and Chan does not teach wherein a top surface of the second integrated circuit die is aligned with the top surface of the dielectric material.
Shibuya teaches an integrated circuit package (¶ 0035: 300) including a top surface of a second integrated circuit die (¶ 0036: 320, similar to 32-1 of Ozawa) aligned with a top surface of a dielectric material (¶ 0041 & fig. 3D: top surface of 320 aligned with top surface of mold compound 302, equivalent to 34 of Ozawa).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the top surface of the second circuit die of Ozawa in view of Foongand Chan to align with the top surface of the dielectric material, as a means to facilitate cooling by allowing direct contact between the die and a heat sink (Shibuya, ¶ 0042). Such a configuration would also reduce manufacturing cost by omitting the second heat spreader of Ozawa.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa as applied to claim 17 above, and further in view of Khandekar et al. (PG Pub. No. US 2011/0233756 A1).
Regarding claim 18, Ozawa teaches the method of claim 17, including depositing thermally conductive material (46).
Ozawa does not teach wherein the thermally conductive material is deposited using a sputtering process.
Khandekar teaches depositing thermally conductive material (¶¶ 0024-0025: 212 and/or 300) by a sputtering process (¶ 0028: thermally conductive coating formed by a sputtering process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Ozawa to include sputtered thermally conductive material, as a means to provide material with high thermal conductivity, facilitating heat dissipation from package by spreading heat away from local hot spots as well as transferring heat from the IC (Khandekar, ¶ 0028: heat spread/dissipated from die 202, similar to 32-1 of Ozawa) to a heat spreader or heat-sink (Khandekar, 602 similar to 36 of Ozawa).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ozawa as applied to claim 16 above, and further in view of Irie.
Regarding claim 19, Ozawa teaches the method of claim 16, including removing material from a top surface of the integrated circuit package (figs. 5D-5E & related text). Ozawa further teaches embodiments including wire bond connectors (col. 7 line 54: 32x) that couple a first integrated circuit die to a package substrate of the integrated circuit package (fig. 7: 32x couples 81-1 and/or 81-2 to substrate 31/41).
Ozawa does not teach wherein the removing material from a top surface of the integrated circuit package is further to expose wire bond connectors that couple the first integrated circuit die to a package substrate of the integrated circuit package.
Irie teaches a method of forming an integrated circuit package (fig. 2B among others) including removing material from a top surface of the integrated circuit package (¶ 0051: material removed from top surface of package member 7) to expose at least a portion of wire bond connectors (¶ 0057: 5a, similar to 32x of Ozawa, include exposed upper portions 8a) that couple an integrated circuit die to underlying structural features (fig. 6: 5a/5b connect chip 3 to underlying support features).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the material removal of Ozawa to expose at least a portion of wire bond connectors, as a means to provide a circuit for monitoring connectivity between cooling device (Irie, ¶ 0022: 13 and/or Ozawa, 36) and the integrated circuit package, improving operation reliability of the package (Irie, ¶ 0042).
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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