DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102, filed 12/19/2025, with respect to the rejection(s) of claim 1 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Peidous, Igor. et al. (Pub No. US 20190139818 A1) (hereinafter, Peidous) in view of Libbert, Jeffery L. (Pub No. US 20180158721 A1) (hereinafter, Libbert).
6. Applicant’s arguments, see Specification, filed 12/19/2025, with respect to the objection of the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Peidous, Igor. et al. (Pub No. US 20190139818 A1) (hereinafter, Peidous), and further in view of Libbert, Jeffery L. (Pub No. US 20180158721 A1) (hereinafter, Libbert).
Peideous, Fig 3: Embodiment of silicon-on-insulator wafer
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Re Claim 1, (Currently Amended) Peidous teaches a substrate (Fig 3) suitable to grow thereon one or more compound semiconductor layers (Suitable to grow silicon germanium layers through epitaxial techniques; ¶[0034]), the substrate comprising the following consecutive parts, from the bottom of the substrate to the top: a base substrate (Semiconductor substrate; 102; Fig 3; ¶[0051]);
a dielectric layer (Relaxed SiGe layer; 104; Fig 3; ¶[0051]) directly on the base substrate, wherein the dielectric layer is a single layer or a stack of multiple dielectric layers (Single layer; Fig 3);
a trap-rich layer (Polycrystalline silicon layer and buried oxide layer; 106/108; Fig 3; ¶0051]) directly on the dielectric layer; and
a crystalline semiconductor layer (Single crystal semiconductor device layer; 110; Fig 3; ¶[0051]) directly on the trap-rich layer.
However, Peidous does not teach wherein the dielectric layer comprises an oxide;
In the same field of endeavor, Libbert teaches wherein the dielectric layer (Insulating layer/dielectric layer; 300/410; Fig 3D; ¶[0055]) comprises an oxide (Silicon dioxide; ¶[0055]). (See Fig 3D blow)
Libbert 1, Fig 3D: Dielectric layer(s) over substrate comprising of oxide in Silicon-on-Insulator structure
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a dielectric layer comprising an oxide, as taught by Libbert for the semiconductor substrate of Peidous. One would have been motivated to do this with a reasonable expectation of success because silicon oxide may reduce parasitic capacitance and prevent leakage current from flowing between the channel and substrate.
Re Claim 2, (Original) Peidous teaches the substrate according to claim 1, wherein the base substrate (Semiconductor substrate; 102; Fig 3; ¶[0051]) is a silicon substrate or a ceramic substrate (Single crystal silicon; ¶[0051]).
Re Claim 3, (Currently Amended) Peidous does not teach the substrate according to claim 1, wherein the dielectric layer is a stack of multiples dielectric layers on the base substrate, said stack comprising a top layer of silicon oxide.
In the same field of endeavor, Libbert teaches the substrate according to claim 1, wherein the dielectric layer is a stack of multiples dielectric layers (Insulating layer/dielectric layer; 300/410; Fig 3D; ¶[0055]) on the base substrate (Semiconductor donor substrate; 400; Fig 3D; ¶[0054]) said stack comprising a top layer of silicon oxide (Silicon dioxide; ¶[0055]).
(Insulating layer/dielectric layer; 300/410; Fig 3D; ¶[0055]) comprises an oxide (Silicon dioxide; ¶[0055]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a stack of dielectric layers on the base substrate, said stack comprising a top layer of silicon oxide, as taught by Libbert for the semiconductor substrate of Peidous. One would have been motivated to do this with a reasonable expectation of success because silicon oxide is a reliable buried oxide (BOX) layer which may reduce parasitic capacitance and prevent leakage current from flowing between the channel and substrate.
Re Claim 4, (Original) Peidous teaches the substrate according to claim 1, wherein the trap-rich layer (Polycrystalline silicon layer and buried oxide layer; 106/108; Fig 3; ¶0051]) is configured to trap free charges above or below the trap-rich layer (Trap charges on handle surface next to the interface of BOX layer; ¶[0024]) .
Re Claim 5, (Original) Peidous teaches the substrate according to claim 1, wherein the trap-rich layer (Polycrystalline silicon layer and buried oxide layer; 106/108; Fig 3; ¶0051]) comprises traps of crystal defects or dopants (May act as a high defectivity layer, therefore comprising of crystal defects; ¶[0012]).
Re Claim 6, (Original) Peidous teaches the substrate according to claim 1, wherein the trap-rich layer (Polycrystalline silicon layer and buried oxide layer; 106/108; Fig 3; ¶0051]) is a layer of polysilicon (Polycrystalline silicon; ¶[0051]).
Re Claim 7, (Original) Peidous teaches the substrate according to claim 1, wherein the trap-rich layer (Polycrystalline silicon layer and buried oxide layer; 106/108; Fig 3; ¶0051]) is a layer of hafnium oxide (A buried oxide layer (dielectric layer) may comprise of hafnium oxide; Claim 17).
Re Claim 8, (Original) Peidous teaches the substrate according to claim 1, wherein the substrate (Semiconductor substrate; 102; Fig 3; ¶[0051]) is suitable to grow thereon one or more layers of one or more III-V semiconductor material(s) (Suitable to grow silicon germanium layers through epitaxial techniques; ¶[0034]).
Re Claim 9, (Original) Peidous teaches the substrate according to claim 1, wherein the crystalline semiconductor layer (Single crystal semiconductor device layer; 110; Fig 3; ¶[0051]) is a crystalline silicon layer (Single crystal, e.g. silicon device layer; ¶[0051]).
9. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Peidous, Igor. et al. (Pub No. US 20190139818 A1) (hereinafter, Peidous) in view of Libbert, Jeffery L. (Pub No. US 20180158721 A1) (hereinafter, Libbert) as applied to claim 1 above, and further in view of Fan, Yonghui et al. (Pub No. CN 111446285 A) (hereinafter, Fan).
Fan, Fig 9: Compound semiconductor layers on silicon substrate
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Re Claim 10, (Original) Peidous in view of Libbert does not teach a substrate according to claim 1, further comprising one or more compound semiconductor layers directly on the crystalline semiconductor layer.
In the same field of endeavor, Fan teaches a substrate (Fig 9) according to claim 1, further comprising one or more compound semiconductor layers (Transition/Intermediate layer; 430/450; Fig 9; ¶[0061]) directly on the crystalline semiconductor layer (Sapphire substrate; 410; Fig 9; ¶[0050]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a substrate comprising one or more compound semiconductor layers directly on the crystalline semiconductor layer, as taught by Fan for the semiconductor substrate of Peidous in view of Libbert. One would have been motivated to do this with a reasonable expectation of success because with compound semiconductor layers on a crystalline semiconductor layer, the lattice constant can better adapt to the substrate and epitaxial layer, reduce dislocations, warpage and cracks caused by lattice mismatch and stress, and improve the performance, product yield and reliability of semiconductor structures, as suggested by Fan (¶[0024]).
Re Claim 11, (Original) Peidous in view of Libbert does not teach the substrate according to claim 10, wherein the one or more compound semiconductor layers are layers of one or more III-V semiconductor material(s).
In the same field of endeavor, Fan teaches the substrate according to claim 10, wherein the one or more compound semiconductor layers (Transition/Intermediate layer; 430/450; Fig 9; ¶[0061]) are layers of one or more III-V semiconductor material(s) (Transition layer 340 is an AlN compound and intermediate layer 450 is composed of any one of gallium indium, indium aluminum nitride, gallium nitride, aluminum nitride, or aluminum indium gallium nitride, preferably aluminum nitride; ¶¶[0052,0057]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used wherein the one or more compound semiconductor layers are layers of one or more III-V semiconductor material(s), as taught by Fan for the semiconductor substrate of Peidous. One would have been motivated to do this with a reasonable expectation of success because with III-V compound semiconductor layers on a crystalline semiconductor layer have a higher forbidden band width than single-crystal layers such as silicon, therefore the wide forbidden band semiconductor has wide application prospect in developing high temperature, high frequency, high power microwave device, anti-radiation device and ultraviolet detector and shortwave light emitting diode and so on, which is an electronic device urgently needed in the fields of wireless communication, national defense, new energy and automatic driving, as suggested by Fan (¶[0045]).
10. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Peidous, Igor. et al. (Pub No. US 20190139818 A1) (hereinafter, Peidous) in view of Libbert, Jeffery L. (Pub No. US 20180158721 A1) (hereinafter, Libbert) as applied to claim 1 above, and further in view of Bajaj, Sanyam et al. (Pub No. US 20230197840 A1) (hereinafter, Bajaj).
Bajaj, Figs 7/8: Singulated portions from III-V compound layers
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Re Claim 20, (Currently Amended) Peidous does not teach a semiconductor chip comprising a singulated portion of the substrate according to claim 1, the chip comprising one or more semiconductor devices produced from one or more compound semiconductor layers grown on the substrate.
In the same field of endeavor, Bajaj teaches a semiconductor chip (Singulated die; 702; Fig 7; ¶[0074]) comprising a singulated portion of the substrate (Integrated circuit device; 800; Fig 8; ¶[0075]) according to claim 1, the chip comprising one or more semiconductor devices (Singulated die; 702; Fig 7; ¶[0074]) produced from one or more compound semiconductor layers (Per ¶[0074] III-V materials may be used to form die substrate 802, which may be a singulated die 702) grown on the substrate.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a semiconductor chip comprising one or more semiconductor devices produced from one or more compound semiconductor layers grown on the substrate, as taught by Bajaj, for the substrate of Peidous One would have been motivated to do this with a reasonable expectation of success because the III-V compound layers singulated into chips may be utilized with an integrated circuit device to combine with a gate and source/drain region to form transistors. Further, III-V transistors such as GaN are particularly beneficial for high-power and high-frequency electronic devices that operate at high temperatures, as suggested by Bajaj (¶[0001]).
Allowable Subject Matter
11. Claims 12-19 are allowed.
12. Regarding Claim 12, the closest prior art of, Libbert, Jeffrey et al. (Pub No. US 20170338143 A1) (hereinafter, Libbert) either singularly or in combination, does not disclose or suggest the combination of limitations including:
“A method of producing a substrate, the method comprising: providing a base substrate;
forming a first dielectric layer directly on the base substrate;
providing a crystalline semiconductor substrate;
forming a trap-rich layer directly on the crystalline semiconductor substrate;
bonding the crystalline semiconductor substrate to the base substrate by bonding a second dielectric layer to the first dielectric layer, or by bonding the trap- rich layer directly to the first dielectric layer; and
removing part of the crystalline semiconductor substrate, leaving a layer of crystalline semiconductor material on the trap-rich layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Referring to Fig 3, Libbert discloses a dielectric layer directly on a crystalline semiconductor substrate which has a part removed, however, it does not disclose a trap-rich layer directly on a crystalline substrate which has a portion removed, therefore claim 12 is allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Wang, Gang et al. (Pub No. CN110178211A) discloses a multilayer semiconductor-on-insulator structure, wherein a handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF device.
[2] Kim, Youngpil et al. (Pub No. WO2023084173A1) discloses a process for preparing a support substrate comprising a charge trapping layer. It also relates to a process for transferring a thin layer onto such a support substrate to form a composite substrate. These support and composite substrates find a significant application in the field of integrated radiofrequency devices, that is to say electronic devices processing signals whose frequency is between about 3 kHz and 300 GHz, for example in the field of telecommunications (telephony , Wi-Fi , Bluetooth...)
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817