DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species II directed to Fig. 5 (Claims 1 and 4-8) in the reply filed on March 3rd, 2026 is acknowledged.
Claim 1 will be allowable if rewritten to overcome the objections. The restriction requirement among Species, as set forth in the Office action mailed on January 13rd, 2026, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of January 13rd, 2026 is withdrawn. Claims 2-3 directed to non-elected Species are no longer withdrawn from consideration because the claim(s) requires all the limitations of an allowable claim.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “the semiconductor device” in lines 29-30 refers back to “a silicon carbide semiconductor device” in line 1 and should be amended to “the silicon carbide semiconductor device” for avoiding confusion.
Claim 1 recites “the device” in line 42 refers back to “a silicon carbide semiconductor device” in line 1 and should be amended to “the silicon carbide semiconductor device” for avoiding confusion.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 6 recites the limitation “the impurity concentration of the second conductivity type” in line 3-4. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claims 1-5 and 7-8 would be allowed if rewritten to overcome the objections, set forth in this Office action.
Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112, set forth in this Office action.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following:
Regarding claim 1, UCHIDA et al (Pub. No.: US 2024/0371766 A1) discloses a silicon carbide semiconductor device in Figs. 1-8, comprising: an insulated gate (51/5) having a metal-oxide-semiconductor structure; a semiconductor substrate (10) containing silicon carbide and having a first main surface and a second main surface that are opposite to each other; a first semiconductor region of a first conductivity type (31), provided in the semiconductor substrate; a second semiconductor region of a second conductivity type (32), provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of the second conductivity type (upper portion of 34), selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, the third semiconductor region having an impurity concentration that is higher than an impurity concentration of the second semiconductor region; a device structure having the insulated gate, wherein a current that passes through a pn junction between the second semiconductor region and the first semiconductor region flows in the device structure; a gate pad (61) provided at the first main surface of the semiconductor substrate via an insulating film (44), the gate pad being electrically connected to a gate electrode (51) constituting the metal of the insulated gate, an entire surface of the gate pad facing the third semiconductor region via the insulating film; a first electrode (62) provided at the first main surface of the semiconductor substrate, apart from the gate pad, the first electrode being electrically connected to the second semiconductor region and the third semiconductor region; a second electrode (53) provided at the second main surface of the semiconductor substrate; a fourth semiconductor region of the second conductivity type (35), provided between the second semiconductor region and the first semiconductor region, the fourth semiconductor region facing the gate pad in a depth direction of the semiconductor device (Z2 direction), and having an impurity concentration that is higher than the impurity concentration of the second semiconductor region and lower than the impurity concentration of the third semiconductor region; a fifth semiconductor region of the second conductivity type (lower portion of 34), penetrating through the second semiconductor region in the depth direction of the semiconductor device and reaching the fourth semiconductor region, the fifth semiconductor region electrically connecting the first electrode to the fourth semiconductor region, and having an impurity concentration that is higher than the impurity concentration of the fourth semiconductor region (see [0136-0179]).
UCHIDA et al fails to disclose a plurality of sixth semiconductor regions of the first conductivity type, selectively provided between the first main surface of the semiconductor substrate and the third semiconductor region, each sixth semiconductor region facing the gate pad in the depth direction of the device.
Claims 2-8 depend on claim 1, and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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