DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 15, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 15, the prior art fails to teach in combination with the rest of the limitations in the claim: “further comprising a fourth circuit coupled to the third circuit, the fourth circuit configured to receive the input clock signal and output a fourth count signal at the predetermined sample rate, wherein the third circuit is configured to generate a fifth signal based on a difference based the first output count signal and the fourth output count signal.”
With respect to claim 20, the prior art fails to teach in combination with the rest of the limitations in the claim: “further comprising a fourth circuit configured to output the third signal as a set of binary encoded bits at a periodic rate.”
Claim 16 is objected to due to its dependency on claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 17-19, 22 and 80 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akondy (U.S. Publication No. 2022/0239312 A1).
With respect to claim 1, Akondy discloses a sensor, comprising:
a first circuit (integrator circuit 210 (integrators 211-213) shown in Fig. 2) configured to receive an input clock signal (see 250 and 252 showing a clock circuit and clock generator shown in Fig. 2; the clock generator 252/clock circuit 250 providing CLKA) and output a first output count (outputting digital integrator output values; col. 2, lines 15-23)
signal at a predetermined sample rate (defined by clock division ratio/clock generator rate);
a second circuit (differentiator circuit 220 or 230 (221-223/231-233 see Fig. 2) configured to receive the input clock signal (clock generator providing CLKB/CLKC) and output a second count (differentiator digital output values; col. 2, lines 15-23)
signal at the predetermined sample rate (defined by same clock generator and division ratio); and
a third circuit (see results circuit 240 shown in Fig. 2) coupled to the first circuit and the second circuit (see first integrator circuit 210 and second circuit 220 connected to the results circuit 240; to provide outputs and results of the two differentiator circuits as states in para 0018, lines 6-8), the third circuit
configured to generate a third signal based the first output count signal and the second output
count signal (para 0018, lines 6-18 which discloses the output signal from the two different differentiator circuits shown in Fig. 2).
With respect to claim 2, Akondy discloses the sensor of claim 1, wherein the first output count signal varies based on a first set of parameters and the second output count signal varies based on a second set of parameters different from the first set of parameters (para 0019, lines 1-12, the clock circuit generates clock signals also called CLKA, CLKB and CLKC).
With respect to claim 3, Akondy discloses the sensor of claim 2, wherein the first set of parameters comprise one or more of temperature and voltage (the system outputs a digital value that represents an analog input to the ADC. That analog input may be a voltage).
With respect to claim 6, Akondy discloses the sensor of claim 1, wherein a frequency of the predetermined sample rate is less than a frequency of the input clock signal (see 250 and 252 showing a clock circuit and clock generator shown in Fig. 2; the clock generator 252/clock circuit 250 providing CLKA).
With respect to claim 17, Akondy discloses the sensor of claim 1, further comprising a substrate comprising the first circuit, the second circuit, and the third circuit (the Akondy reference is an integrated circuit which are fabricated on silicon; there is an unstated semiconductor substrate in the reference).
With respect to claim 18, Akondy discloses the sensor of claim 1, further comprising: a first substrate comprising the first circuit and the second circuit; and a second substrate comprising the third circuit (the Akondy reference is an integrated circuit which are fabricated on silicon; there is an unstated semiconductor substrate in the reference).
With respect to claim 19, Akondy discloses the sensor of claim 1, further comprising a fourth circuit configured to output the third signal as a digital signal (see digital output value 225 shown in para 0018).
With respect to claim 22, Akondy discloses a method of measuring a parameter, comprising:
receiving an input clock signal (see 250 and 252 showing a clock circuit and clock generator shown in Fig. 2; the clock generator 252/clock circuit 250 providing CLKA);
generating a first output count signal at a predetermined rate based on the input clock
signal using a first circuit (see 250 and 252 showing a clock circuit and clock generator shown in Fig. 2; the clock generator 252/clock circuit 250 providing CLKA);
generating a second count signal at the predetermined rate using a second circuit different
from the first circuit (para 0027, lines 1-10); and
generating a third signal based on the first output count signal and the second output
count signal (see first integrator circuit 210 and second circuit 220 connected to the results circuit 240; to provide outputs and results of the two differentiator circuits as states in para 0018, lines 6-8).
With respect to claim 80, Akondy discloses a device configured to monitor blood pressure, the device comprising: an elongate body (see Fig. 2 showing the configuration of the integrated circuit); and
the sensor of claim 1, disposed within a tubular sensor housing, wherein the tubular sensor housing is coupled to the elongate body (see Fig. 2 showing configuration of the integrated circuit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Akondy (U.S. Publication No. 2022/0239312 A1) in view of Johnson et al. (U.S. Publication No. 2021/0275783 A1).
With respect to claim 4, Akondy discloses the sensor of claim 2.
Akondy does not specifically disclose wherein the second set of parameters comprise temperature, voltage, and one or more of force, pressure, light amplitude, audio amplitude, radiation, and a resistance or capacitance corresponding to a chemical or physical reaction.
Johnson et al. discloses wherein the second set of parameters comprise temperature, voltage, and one or more of force, pressure, light amplitude, audio amplitude, radiation, and a resistance or capacitance corresponding to a chemical or physical reaction (para 0031, lines 1-17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Akondy to include wherein the second set of parameters comprise temperature, voltage, and one or more of force, pressure, light amplitude, audio amplitude, radiation, and a resistance or capacitance corresponding to a chemical or physical reaction as taught by Johnoson et al. to predictably compensate for temperature or pressure induced variations in the ADC or improve accuracy.
With respect to claim 5, Akondy discloses the sensor of claim 1.
Akondy does not disclose wherein the third signal corresponds to one or more of temperature, voltage, force, pressure, light amplitude, and audio amplitude.
Johnson et al. discloses wherein the third signal corresponds to one or more of temperature, voltage, force, pressure, light amplitude, and audio amplitude (para 0031, lines 1-17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Akondy to include wherein the third signal corresponds to one or more of temperature, voltage, force, pressure, light amplitude, and audio amplitude as taught by Johnoson et al. to predictably compensate for temperature or pressure induced variations in the ADC or improve accuracy.
(Original) The sensor of claim 1, wherein the first circuit comprises a first
With respect to claim 7, Akondy plurality of delay circuits arranged in a ring configuration, and the second circuit comprises a second plurality of delay circuits arranged in another ring configuration (clocked storage elements (register, accumulators) that are part of the digital filter elements; register 249 shown in Fig. 2).
With respect to claim 8, Akondy discloses the sensor of claim 7, wherein the first plurality of delay circuits comprise a first plurality of inverter circuits (see inverter circuit 256 shown in the clock circuit shown in Fig. 2), and the second plurality of delay circuits comprise a second plurality of inverter circuits, the second plurality of delay circuits different from the first plurality of delay circuits (clocked storage elements (register, accumulators) that are part of the digital filter elements; register 249 shown in Fig. 2).
With respect to claim 9, Akondy discloses the sensor of claim 8, wherein the first circuit comprises a first counter and a first latch, and the second circuit comprises a second counter and a second latch (para 0027, lines 1-10).
With respect to claim 10, Akondy discloses the sensor of claim 8, wherein the first plurality of inverter circuits are coupled to a first multiplexer, and the second plurality of inverter circuits are coupled to a second multiplexer (para 0018, lines 1-9).
With respect to claim 11, Akondy discloses the sensor of claim 8, wherein the first plurality of inverter circuits and the second plurality of inverter circuits are configured in a closed loop with positive
feedback (inverter 256 shown in Fig. 2).
With respect to claim 12, Akondy discloses the sensor of claim 1, wherein the first delay circuit comprises a first resistor-capacitor delay circuit (clocked storage elements (register, accumulators) that are part of the digital filter elements; register 249 shown in Fig. 2).
With respect to claim 13, Akondy discloses the sensor of claim 1, wherein the second circuit comprises one or more of a resistor-capacitor delay circuit, a resistor-inductor delay circuit, and a capacitive delay circuit (para 0027, lines 1-10).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Akondy (U.S. Publication No. 2022/0239312 A1) in view of Uwe et al. (U.S. Publication No. 2013/0208763 A1).
With respect to claim 14, Akondy discloses the sensor of claim 1.
Akondy does not disclose wherein the first circuit comprises a first oscillator circuit, and the second circuit comprises a second oscillator circuit.
Uwe et al. discloses wherein the first circuit comprises a first oscillator circuit, and the second circuit comprises a second oscillator circuit (para 0010, lines 1-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Akondy wherein the first circuit comprises a first oscillator circuit, and the second circuit comprises a second oscillator circuit as taught by Uwe et al. to provide the first and second clock signals that due to a change in the physical quantity one frequency of the first and second frequencies increases, while the other frequency of the first and second frequency decreases.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Akondy (U.S. Publication No. 2022/0239312 A1) in view of Drogi et al. (U.S. Publication No. 2005/0118977 A1).
With respect to claim 21, Akondy discloses the sensor of claim 1.
Akondy does not disclose wherein the fourth circuit comprises one or more of a wire and an antenna.
Drogi et al. discloses wherein the fourth circuit comprises one or more of a wire and an antenna (para 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Akondy to include wherein the fourth circuit comprises one or more of a wire and an antenna as taught by Drogi et al. to predictably allow for a better signal transmission rates over the antenna.
Conclusion
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/FARHANA A HOQUE/ Primary Examiner, Art Unit 2858