The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3 and 6-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the specification for a “storage capacitor electrode”, as recited in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (11,061,290) in view of Takizawa et al. (9,360,726).Regarding claim 1, Tang et al. teach in figure 2 and related text a display panel, comprising a substrate 01 and a plurality of pixels (see figure 23 and related text) arranged on the substrate at intervals, each of the pixels comprising a control area (the area in the location of TFT, as depicted in figure 1) and a pixel area (the area of pixel PITO), and the display panel in the pixel area comprising:
a storage capacitor electrode CFITO1 or CFITO2 (see also figure 3) disposed on the substrate 01;
a pixel electrode PITO disposed on a side of the storage capacitor away from the substrate; and
wherein in the pixel area, the storage capacitor is provided with a through hole 07, and a projection of the through hole on the substrate at least partially overlaps with a projection of the pixel electrode on the substrate.
Tang et al. do not explicitly state using sub-pixels and an isolation layer disposed between the storage capacitor electrode and the pixel electrode.
Takizawa et al. teach in figure 5, 6 and related text a display panel comprising a plurality of subpixels 14 arranged on a substrate at intervals, each of the subpixels comprising a control area (located in the middle of the structure) and a pixel area (located in the edges of the structure), wherein an isolation layer 53 disposed between the storage capacitor electrode and the pixel electrode 14S.
Tang et al. and Takizawa et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tang et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use sub-pixels and to dispose an isolation layer between the storage capacitor electrode and the pixel electrode, as taught by Takizawa et al., in Tang et al.’s device, in order to be able to operate the device in its intended use and in order to prevent short circuit between the storage capacitor electrode and the pixel electrode, respectively.
Regarding claim 3, Takizawa et al. teach in figure 5, 6 and related text and thus the modified device of Tang et al., includes the pixel electrode comprises: a first trunk electrode; a second trunk electrode intersecting with the first trunk electrode, wherein the first trunk electrode and the second trunk electrode divides the pixel area into a first subpixel area, a second subpixel area, a third subpixel area, and a fourth subpixel area; and first branch electrodes, second branch electrodes, third branch electrodes, and fourth branch electrodes disposed in the first subpixel area, the second subpixel area, the third subpixel area, and the fourth subpixel area.
Takizawa et al. do not explicitly state that a profile of the through hole comprises a profile of a first trunk and a second trunk intersecting with each other, and comprises a profile of first branches, second branches, third branches, and fourth branches disposed in the first subpixel area, the second subpixel area, the third subpixel area, and the fourth subpixel area, respectively.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a profile of the through hole comprises a profile of a first trunk and a second trunk intersecting with each other, and comprises a profile of first branches, second branches, third branches, and fourth branches disposed in the first subpixel area, the second subpixel area, the third subpixel area, and the fourth subpixel area, respectively in Tang et al.’s device, in order to improve the device’s characteristics by locating the through hole in the center of the pixel electrode.
Regarding claims 6 and 7, Takizawa et al. teach in figure 5, 6 and related text and thus the modified device of Tang et al., a projection of the first trunk electrode, a projection of the second trunk electrode, a projection of each of the first branch electrodes, a projection of each of the second branch electrodes, a projection of each of the third branch electrodes, and a projection of each of the fourth branch electrodes on the substrate are intersected and perpendicular (as clearly depicted in figure 1) to a projection of the first trunk, a projection of the second trunk, a projection of one of the first branches, a projection of one of the second branches, a projection of one of the third branches, and a projection of one of the fourth branches on the substrate, respectively.
Regarding claim 8, Tang et al. teach in figure 2 and related text a material of the storage capacitor and the pixel electrode is a light-transmitting material ITO.
Regarding claim 9, Tang et al. do not teach that the material of the storage capacitor and the pixel electrode comprises indium tin oxide. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the material of the storage capacitor and the pixel electrode comprises indium tin oxide n prior art’s device in order to simplify the processing steps of making the device by using conventional material.
Regarding claim 10, Tang et al. teach in figure 1 and related text that the display panel in the control area comprises: a thin film transistor device TFT, disposed on the substrate 111 and comprising a gate (un-numbered), a gate insulating layer, an active layer, and a source and drain layer M2; and a common electrode (located on the right side), disposed on the substrate and in a same layer with the gate; and wherein the pixel electrode PITO is electrically connected to the source and drain layer M2, and the storage capacitor CITO is electrically connected to the common electrode.
Regarding claim 11, in the combined device each of the subpixels comprises a first subpixel, a second subpixel, and a third subpixel with different colors, and the first subpixel, the second subpixel, and the third subpixel are a red subpixel, a blue subpixel, and a green subpixel, respectively.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
O.N. /ORI NADAV/
4/22/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights