Prosecution Insights
Last updated: April 19, 2026
Application No. 18/325,083

MODULATION DEVICE

Non-Final OA §103
Filed
May 29, 2023
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
3y 11m
To Grant
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
417 granted / 693 resolved
-7.8% vs TC avg
Strong +21% interview lift
Without
With
+20.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
67 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
14.2%
-25.8% vs TC avg
§112
29.5%
-10.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 693 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Election/Restrictions Applicant's election with traverse of the embodiment of figure 3 in the reply filed on 12/23/2025 is acknowledged. The traversal was not argued. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 6-10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (2019/0013574) in view of Shino et al. (2009/0219263).Regarding claims 1 and 14, Li et al. teach in figure 6A and related text a modulation device, comprising: a substrate 11; a metal layer M1 disposed on the substrate and having at least one hole S2; and a modulation unit (located in modulation zone Z3). Li et al. do not teach one driving element, such that said one driving element disposed on the substrate and overlapped with the at least one hole and wherein said modulation unit electrically connected to the at least one driving element. Shino et al. teach in figure 2A and related text a modulation unit 6 integrated with one driving element. Li et al. and Shino et al. are analogous art because they are directed to devices comprising modulation units and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to integrate the modulation unit of Li et al. with the one driving element (the electronic control of the device), as taught by Shino et al., in Li et al.’s device, in order to reduce the size of the device by providing a single compact package or a single chip, and in order to improve signal integrity, reduce power consumption, and minimize the footprint of high-speed communication systems. Regarding claim 14, Li et al. teach in figure 6A and related text that the metal layer 331 disposed on the substrate and comprising a first portion (directly under area Z5) and a second portion (located at the edge of area Z3), wherein a thickness of the first portion is greater than a thickness of the second portion, and in the combined device, at least one driving element disposed on the substrate and overlapped with the second portion. Regarding claim 2, Li et al. do not teach that the thickness of the metal layer is between 0.5 microns and 2 microns. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the thickness of the metal layer between 0.5 microns and 2 microns in prior art’s device in order to optimize the device characteristics. “It is noted that “change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955)”. See In re Boesch, 617 F.2d 272, 276 (CCPA 1980) (“[Djiscovery of an optimum value of a result effective variable in a known process is ordinarily within the skill of the art.”); In re Aller, 220 F.2d 454, 456 (CCPA 1955) (“where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”)”. Regarding claim 6, Li et al. do not teach that a dimension of the at least one hole is greater than 4 microns and less than 3 microns. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a dimension of the at least one hole is greater than 4 microns and less than 3 microns, in prior art’s device in order to optimize the device characteristics. Regarding claim 7, Li et al. do not teach that at least one hole comprises a plurality of holes, and a minimum distance between two adjacent holes is greater than 3.5 microns. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a minimum distance between two adjacent holes is greater than 3.5 microns in prior art’s device in order to optimize the device characteristics. Regarding the claimed limitations of “at least one hole comprises a plurality of holes” these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. The formation of at least one hole comprises plurality of holes does not produce a structure which is different from a structure which is formed using only one large hole. Regarding claims 8-9 and 16-17, Li et al. do not teach that the metal layer further has a slot, and the modulation unit is at least partially overlapped and traverses the slot. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the metal layer further has a slot, and the modulation unit is at least partially overlapped and traverses the slot in prior art’s device in order to provide better and accurate direction to the radiation pattern. Regarding claims 10 and 18, Li et al. do not teach that a dimension of the slot falls within a range of 500 microns to 600 microns. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a dimension of the slot falls within a range of 500 microns to 600 microns in prior art’s device in order to optimize the device characteristics. Regarding claim 15, Li et al. teach in figure 6A and related text that the thickness of the first portion is less than four times the thickness of the second portion. Claims 3-4 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (2019/0013574) and Shino et al. (2009/0219263), as applied to the claims above, and further in view of Higaki et al. (2016/0204275).Regarding claims 3 and 20, prior art teaches substantially the entire claimed structure, as applied to the claims above except a transparent conductive layer disposed on a drain of the at least one driving element which comprises a thin-film transistor, and the modulation unit is electrically connected to the at least one driving element via the transparent conductive layer. Higaki et al. teach in related text (see e.g. paragraph [0011] a transparent conductive layer (ITO) disposed on a drain of at least one driving element which comprises a thin-film transistor. Higaki, Li et al. and Shino et al. are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a transparent conductive layer disposed on a drain of the at least one driving element which comprises a thin-film transistor, as taught by Higaki et al., in Li et al.’s device, in order to improve the conductivity of the device in a conventional TFT transistor. Regarding the claimed limitation of “the modulation unit is electrically connected to the at least one driving element via the transparent conductive layer”, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect the modulation unit to the at least one driving element via the transparent conductive layer in prior art’s device in order to simplify the processing steps of making the device. Regarding claims 4 and 19, as recited with respect to claim 3, prior art and Higaki et al. teach that the at least one driving element comprises a thin-film transistor, but does not teach that a minimum distance between a semiconductor pattern of the thin-film transistor and the metal layer is greater than 3 microns. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a minimum distance between a semiconductor pattern of the thin-film transistor and the metal layer is greater than 3 microns in prior art’s device in order to optimize the device characteristics. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 2/7/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

May 29, 2023
Application Filed
Jan 28, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+20.6%)
3y 11m
Median Time to Grant
Low
PTA Risk
Based on 693 resolved cases by this examiner. Grant probability derived from career allow rate.

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