Prosecution Insights
Last updated: May 29, 2026
Application No. 18/325,323

TRANSPARENT DISPLAY DEVICE, LAMINATED GLASS, AND MANUFACTURING METHOD OF TRANSPARENT DISPLAY DEVICE

Final Rejection §103
Filed
May 30, 2023
Priority
Dec 07, 2020 — JP 2020-202483 +1 more
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Agc Inc.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
65%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
701 granted / 906 resolved
+9.4% vs TC avg
Minimal -12% lift
Without
With
+-12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
28 currently pending
Career history
949
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
81.9%
+41.9% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
1.6%
-38.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 906 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-8, 10 & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya et al. (US 20140159064) in view of Narukawa et al. (US 20060243988). Regarding claim 1, Sakariya discloses that a transparent display device, comprising: a transparent substrate (para. 0111); and a light-emitting diode element 400 arranged for each pixel on the transparent substrate 100, and a mirror structure 132 formed by power supply lines 102 & 132 (para. 0160, note: “- - since the top conductive contact layer 160 makes electrical contact to reflective via layer 132”, therefore, reflective layer is considered to be a power supply lines) so as to surround the light-emitting diode element (Fig. 10C), a rear-face side of the transparent display device being visually recognizable from a viewing side, and a main surface on the rear-face side in the light-emitting diode element 400 is covered by a light-shielding film 130/132 (Fig. 5A-12C, para. 0124, note: a bottom of light emitting diode element is covered by a light-shielding film since a light reflecting layer has a characteristic of shielding function including aluminum, molybdenum, - -golf, or alloys thereof). Sakariya fails to specify that the light-emitting diode element is a semiconductor chip with an area of 10,000 um2 or less. However, Narukawa suggest that the light-emitting diode element is a semiconductor chip with an area of 10,000 um2 or less (para. 0222, note: 100 micrometer x 100 micrometer or 300 micrometer square). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Sakariya with the light-emitting diode element is a semiconductor chip with an area of 10,000 um2 or less as taught by Narukawa in order to enhance variations of size of LEDs and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 2, Sakariya & Narukawa disclose that the light-shielding film 130/132 is configured to cover an entire main surface on the rear-face side of the light-emitting diode element and formed so as to protrude from the main surface (Sakariya, Fig. 5A-12C). Reclaim 3, Sakariya & Narukawa fail to specify that internal transmittance of visible light in a transparent member positioned more toward the rear-face side than the light-shielding film is 90% or less. However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain internal transmittance of visible light in a transparent member, because it would have been to obtain a certain internal transmittance of visible light in a transparent member to achieve changing visuality (wider or narrow) due to position. Reclaim 4, Sakariya & Narukawa disclose that the transparent substrate is the transparent member (Sakariya, para. 0111). Reclaim 5, Sakariya & Narukawa disclose that a protective layer 150/160 configured to cover the light-emitting diode element on the transparent substrate; and an antireflective film 160/170 formed on the protective layer (Sakariya, Fig. 5A-12C). Reclaim 6, Sakariya & Narukawa disclose that a protective layer 150/160 configured to cover the light-emitting diode element on the transparent substrate, wherein the protective layer is the transparent member (Sakariya , Fig. 5A-12C). Reclaim 7, Sakariya & Narukawa disclose that an antireflective film 170 (a passivation is transparent) formed on a main surface on the viewing side in the transparent substrate (para. 0151, note: a transparent or semi-transparent). Reclaim 8, Sakariya & Narukawa disclose that more toward the rear-face side than the light-shielding film, a light control layer configured to be capable of dynamically adjusting internal transmittance of visible light (Sakariya, Fig. 5A-12C). Reclaim 10, Sakariya & Narukawa disclose that an entire main surface on the viewing side in the light-emitting diode element is covered by a lens. Regarding claim 12, Sakariya & Narukawa disclose that a manufacturing method of a transparent display device of which a rear-face side is visually recognizable from a viewing side, the manufacturing method comprising: arranging a light-emitting diode element 400 being a semiconductor chip having an area of 10,000 um^2or less for each pixel (Narukawa, para. 0222) on a transparent substrate 100; and forming a mirror structure 132 formed by power supply lines 102 & 132 (para. 0160, note: “- - since the top conductive contact layer 160 makes electrical contact to reflective via layer 132”, therefore, reflective layer is considered to be a power supply lines) so as to surround the light-emitting diode element (Fig. 10C); and covering a main surface on the rear-face side in the light-emitting diode element with a light-shielding film 130/132 (Sakariya, Fig. 5A-12C). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya et al. (US 20140159064) in view of Narukawa et al. (US 20060243988) and further in view of Pan (US 20190324577). Regarding claim 11, Sakariya & Narukawa disclose that a laminated glass, comprising: a transparent substrate 100; and a light-emitting diode element 400 arranged for each pixel on the transparent substrate, and a mirror structure 132 formed by power supply lines 102 & 132 (para. 0160, note: “- - since the top conductive contact layer 160 makes electrical contact to reflective via layer 132”, therefore, reflective layer is considered to be a power supply lines) so as to surround the light-emitting diode element (Fig. 10C), a rear-face side of the transparent display device being visually recognizable from a viewing side, the light-emitting diode element is a semiconductor chip with an area of 10,000 um^2 or less (Narukawa, para. para. 0222, note: 100 micrometer x 100 micrometer or 300 micrometer square), and a main surface on the rear-face side in the light-emitting diode element is covered by a light-shielding film 130/132. Sakariya & Narukawa fail to teach that a pair of glass plates (protective layer/polarizer film/ substrate/connection grids in Fig. 3B); and a transparent display device provided between the pair of glass plates (protective layer/polarizer film/ substrate/connection grids in Fig. 3B). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Sakariya & Narukawa with a pair of glass plates; and a transparent display device provided between the pair of glass plates as taught by Pan in order to enhance protection of LED and circuit device and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Response to Arguments With respect to rejected claims under 35 U.S.C. 103, applicant argues that “- - fails to discloses or suggest at least the aforementioned feature - - neither the reflective layer 130 nor the resulting reflective bank layer 132 is a power supply line - -” In response to applicant's contention, it is respectfully submitted that Sakariya discloses all the claimed limitation including the reflective layer or the resulting reflective bank layer 132(130) is a power supply line - -below. Sakariya appears to show, see Fig. 7D-11D, para. 0123, electrical line out 102/132(130) are electrically supply power to as a power supply line. A electrical line out 102 and a reflective layer 132(130) supply a power and electrically conducting to a LED 400, therefore, elements 102/132(130) are considered to be at least a power supply line since a reflective layer 132(130) is electrically conducting to a bottom electrode 420 of a LED 400 in Fig. 5A and the element 132(130) has a reflective characteristic as a mirror (“a reflective layer”). PNG media_image1.png 219 725 media_image1.png Greyscale Therefore, the rejection of claims 1-8 & 10-12 under 35 U.S.C. 103 is deemed proper, and the prima facie case of obviousness has been met. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 30, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection mailed — §103
Jan 09, 2026
Response Filed
Mar 17, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
65%
With Interview (-12.1%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 906 resolved cases by this examiner. Grant probability derived from career allowance rate.

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