DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed 6/24/2026 have been entered and considered. The amendments to claim 1 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 7, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Trimberger et al. US 20170236809 A1 (hereinafter referred to as Trimberger), in view of Lee US 20140175646 A1 (hereinafter referred to as Lee)., in view of Sturcken et al. US 10367415 B1 (hereinafter referred to as Sturcken), and in view of Benson et al. US 20190326234 A1 (hereinafter referred to as Benson)
Regarding claim 1, Trimberger teaches
An integrated circuit (“PMIC die 106 disposed between “IC die 102” para. 0015 FIG. 1) comprising:
a first base (“IC die 102” para. 0015) that has a central area (a central area may be defined as drawn in annotated FIG. 1) and a peripheral area surrounding the central area in a plan view of the integrated circuit (outside of central area in annotated FIG. 1); and
a second base (“PMIC die 106” para. 0015) and that comprises a power amplifier circuit (“circuitry 130” in “PMIC die 106” includes a switching amplifier, para. 0019),
wherein the second base is overlain by the central area, and does not overlap the peripheral area, in the plain view (as defined in annotated FIG. 1, “PMIC die 106” lies within and beneath the central area of “IC die 102”).
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However, Trimberger fails to teach the first base that at least partly comprises a first semiconductor material, second base that at least a partly comprises a second semiconductor material different from the first semiconductor material, wherein the second base includes a semiconductor layer directly joined to a passivation layer of the first base so that the second base is laminated on the first base without an interposed connection member between the semiconductor layer of the second base and the passivation layer of the first base.
Nevertheless, Lee teaches a “second chip 50” with a “second connection substrate 60” on a “first chip 30” with a “first connection substrate 20” (para. 0017 FIG. 1). The “second chip 50” is bonded to “first chip 30” with an “dielectric adhesive sheet 40” formed over “first chip 30” (para. 0028). “First chip 30” with “first connection substrate 20” is bonded to “package substrate 10” through “micro solder balls 27” (para. 0025) while “second chip 50” with “second connection substrate 60” is bonded to “package substrate 10” through “bonding wires 67” (para. 0046). “First chip 30” and “second chip 50” are joined this way instead of through solder balls because solder balls are typically of sizes that render the package height undesirable (para. 0004). Also, thermal stress during operation may more easily induce warpage when solder balls are used (para. 0004). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that joining “IC die 102” to “PMIC die 106” through a “dielectric adhesive sheet 40” and bonding “IC die 102” to “first substrate 104” can further reduce the package height and help prevent package warpage than by using “solder connections 108”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit taught between Trimberger and Sturcken with the base arrangement in Lee. Having the first and second base directly joined through the passivation layer of the first base further reduces the package height and better prevents thermal warpage.
However, Trimberger, modified by Lee, fails to teach the first base that at least partly comprises a first semiconductor material, second base that at least a partly comprises a second semiconductor material different from the first semiconductor material.
Nevertheless, Sturcken teaches
the first base (“processor 200 chip” col 5 lines 3-4 FIG. 2A) that at least partly comprises a first semiconductor material (“the substrate or die for the processor 200 chip can comprise silicon” col 5 lines 16-17), second base (“power management package substrate 220” col 5 lines 4-5) that at least a partly comprises a second semiconductor material different from the first semiconductor material (“power converter chip comprises silicon or gallium nitride” col 3 lines 15-16).
Trimberger and Sturcken teach integrated circuit packages including a power device. The materials of “IC die 102” and “PMIC die 106” are not specified in Trimberger. Meanwhile, Sturcken teaches “processor chip 200” comprising silicon and “power management package substrate 220” comprising gallium nitride. Silicon is a well-known material used for manufacturing dies. With gallium nitride in particular, Benson teaches it as a material suitable for high performance high frequency amplifiers (para. 0036). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon a known material suitable to form “IC die 102” and gallium nitride is suitable to form a high performance “PMIC die 106”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit in Trimberger with the materials taught in Sturcken and Benson. Silicon is well-known for use in die manufacturing and gallium nitride is used for high performance power devices.
Regarding claim 2, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the second base overlaps a center of the first base in the plan view (“PMIC die 106” overlaps the center of “IC die 102” as shown in annotated FIG. 1).
Regarding claim 3, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 2, wherein the power amplifier circuit comprises an amplifier transistor (“PMIC die 106” includes a switching amplifier and the examiner understands switching amplifiers include transistors, para. 0018), and wherein the amplifier transistor overlaps the center of the first base in the plan view (“PMIC 106” is entirely under the center of “IC die 102”, such that the transistor of the switching amplifier is understood to be in the center of “IC die 102”).
Regarding claim 7, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the first base comprises an electric circuit (“solid state circuitry 138 formed in the die 102” para. 0016).
Regarding claim 8, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 7, wherein the electric circuit does not overlap the second base in the plan view (at least portions of “solid state circuitry 138” do not overlap the “PMIC die 106 as seen in annotated FIG. 1 above).
Regarding claim 10, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the first base comprises a first electrode (“contact pad 136”, wherein at least one “contact pad 136” is bonded to “substrate 104”, para. 0016) on a surface of the first base that faces the second base.
Regarding claim 11, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 10, wherein the first electrode is overlain by the peripheral area in the plan view (the “contact pad 136” is overlain by the peripheral area of “IC die 102”).
Regarding claim 12, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the second base comprises a second electrode (“contact pad 142” para. 0022) on a surface of the second base that is opposite a surface that faces the first base (“contact pad 142” face “substrate 104”).
Regarding claim 13, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the power amplifier circuit comprises a circuit device having a collector layer, a base layer, and an emitter layer (is it known that power amplifiers use heterojunction bipolar transistors such as “HBT 15” in Sasaki et al. US 20070190962 A1, heterojunction bipolar transistors comprising a collector, a base layer, and an emitter, Sasaki para. 0006-0009 and 0061), and wherein the collector layer, the base layer, and the emitter layer are laminated, the base layer being between the collector layer and the emitter layer (it is understood the collector, base, and emitter layers are laminated so that electrons and holes can diffuse across each layer, as seen in FIG. 1 para. 0005-0009 of Hase US 20040227155 A1 and FIG. 9 para. 0011 in Tsukao US 20070205432 A1).
However, Trimberger, modified by Lee, Sturcken, fails to teach the collector layer being closer to the first base than the base layer and the emitter layer.
Nevertheless, the laminate structure of a heterojunction bipolar transistor can be stacked in two ways: the collector, base, and then emitter layer or emitter, base, and then collector layer. Both arrangements have the same function given the appropriate connections to each layer. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that either configuration is obvious to try, given that same or similar characteristics are expected for the operation of the heterojunction bipolar transistor. As stated in MPEP 2143 Section E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that having the collector closer to the first base than the base layer or the emitter layer is a possible solution to the predictable result of mounting a heterojunction bipolar transistor in a power amplifier circuit. It is one of two viable options that would have been obvious to try.
Regarding claim 14, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the first semiconductor material has a thermal conductivity greater than the second semiconductor material (as evidenced in “Thermal Conductivity of Common Semiconductors” by Francois Cardelli from Matmake, the thermal conductivity of silicon is around 124 W/(m·K) while the thermal conductivity of GaN is around 65.6 W/(m·K).
Regarding claim 15, Trimberger, modified by Lee, Sturcken and Benson, teach the integrated circuit according to Claim 1, wherein the first semiconductor material is silicon or gallium nitride (“the substrate or die for the processor 200 chip can comprise silicon” Sturcken 12), and wherein the second semiconductor material is gallium arsenide or silicon germanium (gallium arsenide is also taught in Benson para. 0036 as a high performance amplifier material).
Regarding claim 16, Trimberger, modified by Lee, Sturcken and Benson, teach
A radio-frequency module (“exemplary integrated chip package assembly 100” para. 0015) comprising:
the integrated circuit according to Claim 1 (“PMIC die 106 disposed between “IC die 102”); and
a module substrate (“substrate 104” para. 0015) that has a principal surface (“first surface 112” para. 0015), the integrated circuit being on the principal surface (“PMIC die 106” and “IC die “102” are on “substrate 102”),
wherein the first base is joined to the principal surface with a first electrode interposed in between the first base and the principal surface (a “contact pad 136” of “IC die 102”, para 0016), and
wherein the second base is joined to the principal surface with a second electrode interposed in between the second base and the principal surface (a “contact pad 142” under “PMIC die 106”, para. 0022).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Trimberger, modified by Lee, Sturcken and Benson, in view of “Chapter 10: Multi stage amplifier configurations” by Mercer (hereinafter referred to as Mercer).
Trimberger, modified by Lee, Sturcken and Benson the integrated circuit according to Claim 3 but fails to teach wherein the power amplifier circuit is a multistage amplifier circuit, and wherein the amplifier transistor is an output-stage amplifier transistor.
Nevertheless, Mercer teaches that multiple stages of amplification can provide greater gain or bandwidth than a single stage amplification (page 1, first paragraph of included reference). Input and output impedance can be better matched as well. For example, Ida teaches the use of three transistors for signal amplification for radio communication devices (para. 0002), where the final transistor is an output stage transistor (para. 0148). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a multistage amplifier circuit can provide a strong output signal suitable for communications devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Trimberger, Lee, Sturcken, and Benson with the multistage amplifier circuit taught in Mercer and Ida. Multistage amplifier circuits provide increased signal strength for high frequency operations.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Trimberger, in view of Lee, Sturcken and Benson, in view of Sasaki et al. US 20070190962 A1 (hereinafter referred to as Sasaki).
Trimberger, in view of Lee, Sturcken and Benson, teach the integrated circuit according to Claim 7 but fails to teach wherein the electric circuit comprises a control circuit, a first switching circuit, or a second switching circuit, the control circuit being configured to control the power amplifier circuit, the first switching circuit being connected to an output end of the power amplifier circuit, and the second switching circuit being connected to an input end of the power amplifier circuit.
Nevertheless, Sasaki teaches
wherein the electric circuit comprises a control circuit, a first switching circuit, or a second switching circuit (“semiconductor chip 27 is mainly made of silicon, and a control circuit for controlling an amplifier circuit is formed therein” para. 0065 FIG. 4-5), the control circuit being configured to control the power amplifier circuit (the control circuit in “semiconductor chip 27” is for controlling the amplifier circuit in “semiconductor chip 28”, para. 0065-0067), the first switching circuit being connected to an output end of the power amplifier circuit, and the second switching circuit being connected to an input end of the power amplifier circuit.
Trimberger, modified by Lee, Sturcken, Benson and Sasaki, teach integrated circuits comprising power amplifiers. In Trimberger, signals from the circuitry in “IC die 102” control the function of “PMIC die 106” (para. 0020). Meanwhile, Sasaki teaches “semiconductor chip 27” for controlling the amplification of signals from “semiconductor chip 28”; the output signal from “semiconductor chip 28” can be chosen between two different bands by the control current from “semiconductor chip 27” (Sasaki para. 0054-0061). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the control circuit in “semiconductor chip 27” can control the amplifying operation of “PMIC die 106”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the integrated circuit in Trimberger, modified by Lee, Sturcken, Benson with the control circuit taught in Sasaki. The control circuit can determine the operation of the power amplifier circuit, such as selecting the frequency band of the signal output.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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