Prosecution Insights
Last updated: August 17, 2026
Application No. 18/325,708

ELECTRONIC DEVICE WITH WAFER LEVEL CAPACITOR

Non-Final OA §103
Filed
May 30, 2023
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
90%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
77 currently pending
Career history
797
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
66.4%
+26.4% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 16-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield(USPGPUB DOCUMENT: 2021/0272886, hereinafter Bonifield) in view of Jackson (USPGPUB DOCUMENT: 2019/0341885, hereinafter Jackson). Re claim 1 Bonifield discloses in Fig 1, 2, 3 an electronic device comprising: a leadframe having a die pad(160a) and leads(424); a die(120) attached to the die pad(160a), the die(120) including an active side(by way of 122a)[0021], the die(120) further including a dielectric layer(136)[0008] deposited on a side of the die(120) opposite that of the active side(by way of 122a)[0021] and a die attach film(156/152) deposited on the dielectric layer(136)[0008]; and a wire bond(151) attached from the active side(by way of 122a)[0021] of the die(120) to the die pad(160a); a mold compound(160), wherein a stacked formation of the die(120), the dielectric layer(136)[0008], and the die attach film(156/152) form a capacitor(100)[0032] that filters noise(since 100 demodulates or extracts this may be interpreted as filters)[0005,0031] from a signal carried by the wire bond(151). Bonifield does not specifically teach a mold compound(160) encapsulating the die(120), the wire bond(151), and a portion of the leadframe, Jackson discloses a mold compound(135) encapsulating the die(130), the wire bond(144/143), and a portion of the leadframe[claim 10], It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Jackson to the teachings of Bonifield in order to improve the overall package performance [0006, Jackson]. Re claim 2 Bonifield and Jackson disclose the electronic device of claim 1, wherein the die(120) includes an electrically grounded and conductive substrate on the side opposite the active side(by way of 122a)[0021] that forms one electrically conductive plate of the capacitor(100)[0032]. Re claim 3 Bonifield and Jackson disclose the electronic device of claim 2, wherein the die attach film(156/152) is an electrically conductive film that along with the die pad(160a) forms another electrically conductive plate of the capacitor(100)[0032]. Re claim 4 Bonifield and Jackson disclose the electronic device of claim 1, wherein the dielectric layer(136)[0008] is comprised of an oxide and is deposited on the side opposite the active side(by way of 122a)[0021] of the die(120) via a spin coating process. Re claim 5 Bonifield and Jackson disclose the electronic device of claim 1, wherein the signal is one of a reference voltage[0006,0028] and an output signal. Re claim 16 Bonifield discloses in Fig 1, 2, 3 an electronic device comprising:a leadframe having a die pad(160a) and leads(424);a die(120) attached to the die pad(160a), the die(120) including an active side(by way of 122a)[0021] and a non-active side(side attached to 136) opposite that of the active side(by way of 122a)[0021];a die attach film(156/152) attached to the non-active side(side attached to 136) of the die(120) that facilitates attachment of the die(120) to the die pad(160a);a wire bond(151) attached from the active side(by way of 122a)[0021] of the die(120) to the die pad(160a);a mold compound(160), wherein a stacked formation of the die(120), the die attach film(156/152), and the die pad(160a) form a capacitor(100)[0032] that filters noise(since 100 demodulates or extracts this may be interpreted as filters)[0005,0031] from a signal carried by the wire bond(151). Bonifield does not specifically teach a mold compound(160) encapsulating the die(120), the wire bond(151), and a portion of the leadframe, Jackson discloses a mold compound(135) encapsulating the die(130), the wire bond(144/143), and a portion of the leadframe[claim 10], It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Jackson to the teachings of Bonifield in order to improve the overall package performance [0006, Jackson]. Re claim 17 Bonifield and Jackson disclose the electronic device of claim 16, wherein the die attach film(156/152) is made from a die(120)lectric material that forms a dielectric layer(136)[0008] of the capacitor(100)[0032]. Re claim 18 Bonifield and Jackson disclose the electronic device of claim 17, wherein the die(120) includes an electrically grounded and conductive substrate on the non-active side(side attached to 136) that forms one electrically conductive plate of the capacitor(100)[0032]. Re claim 19 Bonifield and Jackson disclose the electronic device of claim 18, wherein the die pad(160a) forms another electrically conductive plate of the capacitor(100)[0032]. Re claim 20 Bonifield and Jackson disclose the electronic device of claim 16, wherein the signal is one of a reference voltage[0006,0028] and an output signal. Re claim 21 Bonifield discloses in Fig 1, 2, 3 a packaged integrated circuit (IC) comprising:a leadframe having a die pad(160a) and leads(424);a die(120) attached to the die pad(160a) via an insulation material(136)[0008];a wire bond(151) electrically coupled between the die(120) to the die pad(160a); and a mold compound(160). Bonifield does not specifically teach a mold compound(160) encapsulating the die(120), the wire bond(151), and at least a portion of the leadframe. Jackson discloses a mold compound(135) encapsulating the die(130), the wire bond(144/143), and at least a portion of the leadframe[claim 10]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Jackson to the teachings of Bonifield in order to improve the overall package performance [0006, Jackson]. Re claim 22 Bonifield and Jackson disclose the packaged IC of claim 21, wherein the insulation material includes a dielectric layer(136)[0008]. Re claim 23 Bonifield and Jackson disclose the packaged IC of claim 21, further comprising a die attach film(156/152) between the insulation material and the die pad(160a). Re claim 24 Bonifield and Jackson disclose the packaged IC of claim 23, wherein the die attach film(156/152) is an electrical conductor. Response to Arguments Applicant’s arguments with respect to claim(s) 1-5, 16-24 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 30, 2023
Application Filed
Aug 03, 2023
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12708031
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
3y 1m to grant Granted Aug 11, 2026
Patent 12702000
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 5m to grant Granted Aug 04, 2026
Patent 12701980
Layer-By-Layer Formation Of Through-Substrate Via
3y 4m to grant Granted Aug 04, 2026
Patent 12701999
SEMICONDUCTOR POWER MODULE
3y 0m to grant Granted Aug 04, 2026
Patent 12696782
ELECTRICAL TRACES ON GLASS CORES IN INTEGRATED CIRCUIT PACKAGES AND METHODS OF MANUFACTURING THE SAME
4y 7m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month