Prosecution Insights
Last updated: April 19, 2026
Application No. 18/325,708

ELECTRONIC DEVICE WITH WAFER LEVEL CAPACITOR

Non-Final OA §103
Filed
May 30, 2023
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
645 granted / 715 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
63 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 715 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-5, 16-20 in the reply filed on 10/13/25 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manack(USPGPUB DOCUMENT: 2022/0415762, hereinafter Manack) in view of Cook (USPGPUB DOCUMENT: 2019/0081133, hereinafter Cook). Re claim 1 Manack discloses an electronic device comprising: a leadframe having a die pad(114/112) and leads; a die(120) attached to the die pad(114/112), the die(120) including an active side[0014]; and a wire bond(118) attached from the active side[0014] of the die(120) to the die pad(114/112); a mold compound(116) encapsulating the die(120), the wire bond(118), and a portion of the leadframe, wherein a stacked formation of the die(120). Manack does not disclose the die(120) further including a dielectric layer deposited on a side of the die(120) opposite that of the active side[0014] and a die(120) attach film deposited on the dielectric layer; the dielectric layer, and the die(120) attach film form a capacitor that filters noise from a signal carried by the wire bond(118) Cook disclose the die(201) further including a dielectric layer(210) deposited on a side of the die opposite that of the active side(top) and a die attach film(237) deposited on the dielectric layer; the dielectric layer, and the die attach film form a capacitor(231/232) that filters noise [0019,0023] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Manack in order to provides an increased level of safety [0005, Cook]. In doing so, the die(201) further including a dielectric layer(210) deposited on a side of the die opposite that of the active side[0014] and a die attach film(237) deposited on the dielectric layer; the dielectric layer, and the die attach film form a capacitor(231/232) [0019,0023] that filters noise from a signal[0022 of Cook] carried by the wire bond(118 of Manack) Re claim 2 Manack and Cook disclose the electronic device of claim 1, wherein the die(120) includes an electrically grounded and conductive substrate on the side opposite the active side[0014] that forms one electrically conductive plate of the capacitor (231/232 of Cook). Re claim 3 Manack and Cook disclose the electronic device of claim 2, wherein the die(120) attach film is an electrically conductive film that along with the die pad(114/112) forms another electrically conductive plate of the capacitor (231/232 of Cook). Re claim 4 Manack and Cook disclose the electronic device of claim 1, wherein the dielectric layer is comprised of an oxide and is deposited on the side opposite the active side[0014] of the die(120) via a spin coating process. Re claim 5 Manack and Cook disclose the electronic device of claim 1, wherein the signal[0022 of Cook] is one of a reference voltage and an output signal[0022 of Cook]. Re claim 16 Manack discloses an electronic device comprising:a leadframe having a die pad(114/112) and leads; a die(120) attached to the die pad(114/112), the die(120) including an active side[0014] and a non-active side[0014] opposite that of the active side[0014]; a wire bond(118) attached from the active side[0014] of the die(120) to the die pad(114/112); a mold compound(116) encapsulating the die(120), the wire bond(118), and a portion of the leadframe, Manack does not disclose a die(120) attach film attached to the non-active side[0014] of the die(120) that facilitates attachment of the die(120) to the die pad(114/112); wherein a stacked formation of the die(120), the die(120) attach film, and the die pad(114/112) form a capacitor that filters noise from a signal carried by the wire bond(118). Cook disclose a die attach film(237) attached to the non-active side(bottom) of the die(201) that facilitates attachment of the die(201) to the die pad(221); wherein a stacked formation of the die(201), the die attach film(237), and the die pad(221) form a capacitor(231/232) that filters noise[0019,0023] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Manack in order to provides an increased level of safety [0005, Cook]. In doing so, a die attach film(237) attached to the non-active side(bottom) of the die(201) that facilitates attachment of the die(201) to the die pad(221); wherein a stacked formation of the die(201), the die attach film(237), and the die pad(221) form a capacitor(231/232) [0019,0023] that filters noise from a signal[0022 of Cook] carried by the wire bond(118 of Manack). Re claim 17 Manack and Cook disclose the electronic device of claim 16, wherein the die(120) attach film is made from a dielectric material that forms a dielectric layer of the capacitor (231/232 of Cook). Re claim 18 Manack and Cook disclose the electronic device of claim 17, wherein the die(120) includes an electrically grounded and conductive substrate on the non-active side[0014] that forms one electrically conductive plate of the capacitor (231/232 of Cook). Re claim 19 Manack and Cook disclose the electronic device of claim 18, wherein the die pad(114/112) forms another electrically conductive plate of the capacitor (231/232 of Cook). Re claim 20 Manack and Cook disclose the electronic device of claim 16, wherein the signal[0022 of Cook] is one of a reference voltage and an output signal[0022 of Cook]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 30, 2023
Application Filed
Aug 03, 2023
Response after Non-Final Action
Jan 23, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604686
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604749
SEMICONDUCTOR PACKAGE
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Patent 12598990
ELECTRICALLY ISOLATED DISCRETE PACKAGE WITH HIGH PERFORMANCE CERAMIC SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
Patent 12598986
METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)
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Patent 12593675
RETICLE STITCHING TO ACHIEVE HIGH-CAPACITY INTEGRATED CIRCUIT
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 715 resolved cases by this examiner. Grant probability derived from career allow rate.

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