DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 05/31/2023. Claims 1-18 are pending in the Application, of which Claims 1, 9 and 14 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/31/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show descriptive legends for functional blocks 210, 220, 510, 530, 520, 730, 740 and 710, as described in the specification. Suitable descriptive legends may be used subject to approval by the Office, or may be required by the examiner where necessary for understanding of the drawing. They should contain as few words as possible.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita (U.S. Patent No. 6,378,098) Pub. Date: 2002-04-23.
Regarding independent Claims 1, 9 and 14 ,Yamashita discloses a semiconductor test system for efficiently testing semiconductor integrated circuits having PLL (phase lock loop) circuits, comprising:
an analog circuit, and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to provide an analog signal and the digital circuit is configured to provide a digital signal; FIG. 1 corresponding to a “mixed-signal circuit” is a semiconductor test system for testing an IC device (DUT) 40 having a PLL (phase lock loop) circuit.
FIG. 3 shows a structure for testing an IC device having a phase lock loop circuit by a semiconductor test system. In this example, an IC device under test (DUT) 40 includes a phase lock loop (PLL) circuit 45 to produce an internal clock (PLL clock) signal based on a clock signal received at a clock pin 41.
An example of a PLL circuit is shown in FIG. 5 which is comprised of a phase detector (phase comparator) 46 “analog circuit”, a loop filter 47 “digital circuit” and a voltage controlled oscillator (VCO) 48“analog circuit”. Typically, the loop filter 47 is a low pass filter formed by analog or digital components.
a test signal generator configured to generate a test signal and provide the test signal to the digital circuit during a test operation mode; FIG. 1. The pattern generator 20 generates pattern data PTA 600 which includes test pattern data 620 to be applied to the data pin 42 of the DUT 40 and the expected data (not shown) to compare the resultant output of the DUT 40.
wherein the mixed-signal circuit is tested based on an output of the digital circuit generated in response to the test signal. The IC tester receives output signals from the IC device under test generated in response to the test pattern data. The output signals are sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly. The clear signal 300 is to clear (reset) the previous data setting before starting the next set (block) of test patterns. The pattern generator 20 generates the pattern data 600 which includes test data 620 to be applied to the data pin 42 of the DUT 40 and the expected data (not shown) to compare the resultant output of the DUT 40.
Regarding Claims 2, 10, 15, Yamashita discloses the test signal generator to generate the test signal. FIG. 1 The pattern generator 20 generates pattern data PTA 600 which includes test pattern data 620 to be applied to the data pin 42 of the DUT 40 and the expected data (not shown) to compare the resultant output of the DUT 40.
Regarding Claim 5, Yamashita discloses a controller to generate a start signal indicating the start of the test operation mode. The clear signal 300 is to clear the previous data setting before starting the next set (block) of test patterns. Before the start of the test pattern (pattern start) of a test pattern block, the previous data in the clock and waveform generators 30.sub.0 and 30.sub.1 is cleared (reset) by the clear signal 300.
Regarding Claims 4, 12, 17, Yamashita discloses deactivate the analog circuit during the test operation mode. FIG. 1. The AND gate 37 is provided with the clear signal 300 and the gate signal 400 at its input and an output thereof is connected to the terminal B of the multiplexer 32. The clear signal 300 is also directly provided to the terminal A of the multiplexer 32.
Regarding Claims 3, 11, 16, Yamashita discloses generate a pass or fail signal based on a comparison of the received output signal. The IC tester receives output signals from the IC device under test generated in response to the test pattern data. The output signals are sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly “pass or fail”. The pattern generator 20 generates the pattern data 600 which includes test data 620 to be applied to the data pin 42 of the DUT 40 and the expected data (not shown) to compare the resultant output of the DUT 40.
Regarding independent Claims 6, 13, 18, Yamashita discloses record the voltage waveform of the signals supplied to the circuits. The embodiment of the present invention is explained with reference to FIGS. 1 and 2. The clock and waveform generator 30.sub.0 produces a clock signal 120 which is applied to the clock pin 41 of the DUT 40. The clock and waveform generator 30.sub.1 generates the test pattern data 620 which is applied to the data pin 42 of the DUT 40. The clock signal 120 is produced based on the reference clock RCLK and the tester rate signal 200. The test pattern data 620 is produced based on the pattern data 600 with use of the reference clock RCLK 100 and the tester rate signal 200.
Regarding Claims 7, 8, Yamashita discloses the mixed-signal circuit is a digital phase-lock loop circuit. FIG. 5 shows a basic structure of a PLL (phase lock loop) circuit. FIG. 3 shows a structure for testing an IC device having a phase lock loop circuit by a semiconductor test system. In this example, an IC device under test (DUT) 40 includes a phase lock loop (PLL) circuit 45 to produce an internal clock (PLL clock) signal based on a clock signal received at a clock pin 41.
The phase detector 46 compares the phase of an input clock signal (CLK) and an oscillation signal (PLL CLK) of the VCO 48 and produces an phase error signal which represents a phase difference between the two signals. Upon receiving the phase error signal from the phase detector 46, the loop filter 47 converts the phase error signal to an averaged DC voltage. Typically, the loop filter 47 is a low pass filter formed by analog or digital components. The VCO 48 is an oscillator wherein the oscillation frequency is controlled by the averaged DC voltage of the loop filter 47.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 4, 2026
Non-Final Rejection 20260803
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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