DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 3, filed 15 June 2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Pagaila (U.S. 2013/0015577) in view of Briere et al. (U.S. 9,449,899).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
plurality of QFN side connections forming at least part of all side surfaces of the chip-scale QFN plastic integrated circuit package,
PCB,
RF and DC connections of the PCB,
thermal contact surface with the PCB, and
plurality of direct contact connections that connect…to...the at least one QFN base connection
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
The claim recites “wherein the chip-scale QFN plastic integrated circuit package comprising:” in line 2 of the claim… should be “comprises”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitation of “…side connections forming at least part of all side surfaces of the…package”. There is only disclosure for “multiple QFN side connections…configured to be located on all side surfaces of the integrated circuit” [0021], [0030].
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitation of “wherein the at least one connection layer reduces a thermal expansion coefficient difference between the at least one semiconductor chip and the at least one QFN base connection”. There is only disclosure for “the connection layer (7) is configured to be manufactured from materials with a thermal expansion coefficient that will dampen the thermal expansion coefficient difference between the semiconductor chip (5) and the QFN packaging base” [0034] with no further description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 and depending claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the limitation “…side connections forming at least part of all side surfaces of the…package” renders the claim indefinite, as it is unclear if the side connections form part of each of every side surface of a part of the collective of side surfaces.
Regarding Claim 1, the limitation “…side connections forming at least part of all side surfaces of the…package”, in combination with the limitations of “wherein the side surfaces of the chip-scale QFN plastic integrated circuit package have a respective surface normal that is perpendicular to a surface normal of a base surface of the chip-scale QFN plastic integrated circuit package” renders the claim indefinite, as the base surface is one of all side surfaces. For purposes of examination, the claim will be interpreted to mean that the plurality of QFN side connections form part of opposing side surfaces of the chip-scale QFN plastic integrated circuit package, said opposing side surfaces being perpendicular to the base surface of the chip-scale QFN plastic integrated circuit package.
Regarding Claim 1, the limitation of “of all side surfaces of the…package” in combination with “the side surfaces…have a respective surface normal that is perpendicular to a surface normal of a base surface” renders the claim indefinite, as it is unclear if each side surface needs to be perpendicular to the base surface to meet the limitation or if a single side surface of the plurality of side surfaces being perpendicular to the base surface would meet the limitation. Furthermore, the base surface is a side surface of the package and therefore would be encompassed in “all side surfaces of the…package” and therefore it is unclear how the base surface can be perpendicular to itself.
Claim 1 recites the limitation “[a]t least one protective coating…the protective coating” in Line 9, “[at] the side surfaces” in Line 9, “the PCB” in Line 10, and “[t]he side surfaces of the…package” in Line 11. There is insufficient antecedent basis for these limitations in the claim.
Claim 5 recites the limitation of “wherein the at least one connection layer reduces a thermal expansion coefficient difference between the at least one semiconductor chip and the at least one QFN base connection” which renders the claim indefinite. It is unclear what “reducing” the difference in CTE between two elements by a third, separate element entails. For purposes of examination, that claim will be interpreted to mean thermally connecting the at least one semiconductor chip and QFN base connection.
Claim 7 recites “where the at least one conductive back surface layer is configured to facilitate a thermal energy dissipation of the at least one semiconductor chip in combination with the at least one connection layer”, which renders the claim indefinite as it is not clear if the claim requires the conductive back layer and the at least one connection layer to facilitate thermal energy dissipation of the at least on semiconductor chip or the at least one conductive back surface layer facilitates dissipation of thermal energy of the at least one semiconductor chip and the at least one connection layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila (U.S. 2013/0015577) in view of Briere et al. (U.S. 9,449,899).
Regarding Claim 1, Pagaila Figure 11b discloses a chip-scale quad flat no-lead (QFN) plastic integrated circuit package, wherein the chip-scale QFN plastic integrated circuit package comprising:
- at least one semiconductor chip configured to process radio frequency (RF) signals (chip 124, [0042]);
- at least one protective coating, configured to form an outer layer of the chip-scale QFN plastic integrated circuit package and to protect the at least one semiconductor chip against external influences (protective coating 204);
- a plurality of QFN side connections forming at least a part of all side surfaces of the chip- scale QFN plastic integrated circuit package, wherein said plurality of QFN side connections are exposed outside of the protective coating and are configured to connect, at the side surfaces of the chip-scale QFN plastic integrated circuit package, RF and direct current (DC) connections on the PCB to the at least one semiconductor chip, wherein the side surfaces of the chip-scale QFN plastic integrated circuit package have a respective surface normal that is perpendicular to a surface normal of a base surface of the chip-scale QFN plastic integrated circuit package (QFN side connections 222a/222c);
- at least one QFN base connection providing the base surface of the chip-scale QFN plastic integrated circuit package configured to ensure connection of at least one of the RF and/or DC connections on the PCB to the at least one semiconductor chip and configured to provide a thermal contact surface with the PCB (QFN base connection 222b),
- at least one connection layer establishing an electrical, thermal and physical connection between the at least one semiconductor chip and the at least one QFN base connection (connection layer 226 or 134 or 132);
- at least one conductive back surface layer establishing an electrical and thermal connection between the at least one semiconductor chip and the at least one QFN base connection (conductive back surface layer 134 or 132 or 226);
- a plurality of direct contact connections that connect the at least one semiconductor chip to the plurality of QFN side connections and the at least one QFN base connection (direct contact connections 132 or 226 or 134).
However, Pagaila does not explicitly disclose “at least one on-chip protective layer located on the at least one semiconductor chip and configured to physically protect an upper part of the at least one semiconductor chip”. In the same field of endeavor, Briere et al. discloses an encapsulated QFN package wherein a plurality of QFN side connections and a QFN base connection are electrically connected to at least one semiconductor chip with at least one on-chip protective layer formed thereon and configured to physically protect an upper part of the at least one semiconductor chip (Briere et al., chip 12, QFN side connections 10, QFN base connection 22, encapsulation 20, protective layer 18/16, Figure 1). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one on-chip protective layer located on the at least one semiconductor chip and configured to physically protect an upper part of the at least one semiconductor chip in Pagaila in view of Briere et al. in order to avoid adverse effects on the operation of the die (Briere et al., Column1, Lines 24-29).
Regarding Claim 5, Pagaila in view of Briere et al. further discloses the chip-scale QFN plastic integrated circuit package according to claim 1, wherein the at least one connection layer has a thermal expansion coefficient, wherein the at least one connection layer reduces a thermal expansion coefficient difference between the at least one semiconductor chip and the at least one QFN base connection (Pagaila, Figure 11b, connection layer 226 or 134 or 132, semiconductor chip 124, QFN base connection 222b, [0047], [0055], [0043], [0041], and [0045]).
Regarding Claim 6, Pagaila in view of Briere et al. further discloses the chip-scale QFN plastic integrated circuit package according to claim 1, wherein the at least one conductive back surface layer is configured to mechanically support an electrical connection of the plurality of direct contact connections of the at least one semiconductor chip (Pagaila, Figure 11b, conductive back surface layer 134 or 132 or 226, direct contact connections 132 or 226 or 134, semiconductor chip 124, [0056], and [0072]).
Regarding Claim 7, Pagaila in view of Briere et al. further discloses the chip-scale QFN plastic integrated circuit package according to claim 1, wherein the at least one conductive back surface layer is configured to facilitate a thermal energy dissipation of the at least one semiconductor chip in combination with the at least one connection layer (Pagaila, Figure 11b, conductive back surface layer 134 or 132 or 226, connection layer 226 or 134 or 132, semiconductor chip 124).
Regarding Claim 8, Pagaila in view of Briere et al. further discloses the chip-scale QFN plastic integrated circuit package according to claim 1, wherein the plurality of direct contact connections are configured to connect the at least one semiconductor chip to the plurality of QFN side connections and the at least one QFN base connection by creating an interface with the at least one conductive back surface layer and the at least one connection layer (Pagaila, Figure 11b, direct contact connections 132 or 226 or 134, semiconductor chip 124, QFN side connections 222a/222c, conductive back surface layer 134 or 132 or 226, connection layer 226 or 134 or 132)
Regarding Claim 18, Pagaila in view of Briere et al. further discloses the chip-scale QFN plastic integrated circuit package according to claim 5, wherein the at least one conductive back surface layer is configured to mechanically support an electrical connection of the plurality of direct contact connections of the at least one semiconductor chip (Pagaila, Figure 11b, conductive back surface layer 134 or 132 or 226, direct contact connections 132 or 226 or 134, semiconductor chip 124, [0056], and [0072]).
Response to Arguments
Regarding the objection to the drawings for not showing “a plurality of direct contact connection that connect the at least one semiconductor chip to…the at least one QFN base connection”, the Applicant argues “the direct contact connections 9 connect the semiconductor chip 6 to the QFN base connection 4 via the connection layer 7 and conductive back surface layer 8”. However, the portions of the connection layer 7 and conductive back surface layer 8 that the direct contact connections 9 are coupled to are not coupled to the portion of the connection layer 7 and conductive back surface layer 8 that the QFN base connection 4 is coupled to. The drawings show those different portions of the connection layer 7/back surface layer 8 being isolated from one another. Therefore, the arguments are not persuasive and the drawings objection persists.
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Paek (U.S. 6,700,187) discloses a QFN package wherein at least one semiconductor chip is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Abbott (U.S. 2004/0183166) discloses a QFN package wherein at least one semiconductor chip is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Lee et al. (U.S. 8,405,230) discloses a QFN package wherein at least one semiconductor chip having a protective layer is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Lee (U.S. 7,691,681) discloses a QFN package wherein at least one semiconductor chip is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Xia et al. (U.S. 9,515,010) discloses a QFN package wherein at least one semiconductor chip is encapsulated in a protective coating and is connected to a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Fujii (U.S. 2020/0144211) discloses a QFN package wherein at least one semiconductor chip having a protective layer is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Futamara et al. (U.S. 12,166,002) discloses a QFN package wherein at least one semiconductor chip having a protective layer is encapsulated in a protective coating and is connected to a QFN base connection and a plurality of QFN side-exposed connections through a connection layer, conductive back surface layer, and a plurality of direct contact connections.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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