DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 recites the limitation “the second trench gate electrode” in line 6. Claims 13 and 16 recite the limitation "the gate insulating layer" in lines 12-13 and line 9, respectively. There is insufficient antecedent basis for these limitations in the claim. These claims will, however, be examined as best understood.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-7 and 9-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0384329 A1 to Kim (hereinafter “Kim” – previously cited reference) in further view of US 2021/0202724 A1 to Rahimo (hereinafter “Rahimo” – previously cited reference).
Regarding claim 1, Kim discloses an insulated gate bipolar transistor comprising:
a collector electrode (IGBT 1 having collector electrode 110; Fig. 3; paragraphs [0051]-[0052]);
a collector on the collector electrode (collector layer 120 disposed on collector electrode 110; Fig. 3; paragraph [0052]);
a drift region on the collector (drift region 140 on collector layer 120; Fig. 3; paragraph [0052]);
a plurality of first trench gates spaced apart from each other in the drift region (first and second trench gates 160 spaced apart in drift region 140; Fig. 3; paragraph [0054]);
a floating first body region between first adjacent ones of the first trench gates and in the drift region (floating first portion of body region 150 between first adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
a second body region between second adjacent ones of the first trench gates and in the drift region (second portion of body region 150 between second adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]); and
a planar gate including a gate insulating layer on the first body region and a gate electrode on the gate insulating layer (planar top portion of gate 160 having gate insulating film 161 disposed adjacent first body region 150 and gate electrode 163 disposed on film 161; Fig. 3; paragraph [0055]).
Kim fails to disclose wherein a lowermost surface of the first body region is deeper in the drift region than a lowermost surface of the second body region; a planar gate between the first adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates, the planar gate including a gate insulating layer on an uppermost surface of the first body region and a gate electrode on the gate insulating layer.
However, the relative difference in the depth between the first and second body regions is not claimed and therefore would include very minor differences in depths which will occur during fabrication of the two regions given inherent error in manufacturing processes. Further, significant differences in depth between the regions is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower on-state resistance, improved switching performance, and enhanced breakdown voltage.
Kim, as modified, fails to disclose a planar gate between the first adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates, the planar gate including a gate insulating layer on an uppermost surface of the first body region and a gate electrode on the gate insulating layer.
However, Rahimo discloses a planar gate between the first adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates (planar gate electrode 10 disposed between adjacent trench gate electrodes 11 and portions of planar gate electrode 10 do not overlap with trench gate electrodes 11; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]), the planar gate including a gate insulating layer on an uppermost surface of the first body region and a gate electrode on the gate insulating layer (planar gate electrode 10 having insulating layer 12 on upper surface of base layer 9 and electrode on insulating layer 12; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]).
Kim and Rahimo are both considered to be analogous to the claimed invention because they are in the same field of IGBTs. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teaching of Rahimo in order to potentially provide reduced on-state voltage drop and conduction losses, improved trade-off between on-state and turn-off losses, and enhanced reliability and breakdown voltage management.
Regarding claim 2, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 1. Kim further discloses further comprising: an interlayer insulating layer covering the planar gate, the first body region and the second body region; and an emitter electrode on the interlayer insulating layer (interlayer insulating film 170 disposed over planar top portion of gate 160 and first and second portions of body region 150, where emitter electrode 190 is disposed over film 170 and first portion of body region 150 is floating; Fig. 3; paragraph [0056]).
Regarding claim 4, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 2. Kim further discloses further comprising: an emitter in the second body region; and a body contact in the second body region, wherein the emitter is electrically connected to the emitter electrode (second portion of body region 150 having emitter 181 and contact region 183, where emitter 181 is electrically connected to emitter electrode 190; Fig. 3; paragraph [0056]).
Regarding claim 6, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 2. Kim further discloses further comprising a buffer layer on the collector (buffer layer 130 disposed upon collector layer 120; Fig. 3; paragraph [0052]).
Regarding claim 7, Kim discloses an insulated gate bipolar transistor comprising:
a collector electrode (IGBT 1 having collector electrode 110; Fig. 3; paragraphs [0051]-[0052]);
a collector on the collector electrode (collector layer 120 disposed on collector electrode 110; Fig. 3; paragraph [0052]);
a drift region on the collector (drift region 140 on collector layer 120; Fig. 3; paragraph [0052]);
a plurality of first trench gates spaced apart from each other in the drift region (first and second trench gates 160 spaced apart in drift region 140; Fig. 3; paragraph [0054]);
a floating first body region between adjacent ones of the first trench gates and in the drift region (first portion of body region 150 between first adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
a second body region between different adjacent ones of the first trench gates and in the drift region (second portion of body region 150 between second adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
a planar gate including a gate insulating layer on the first body region and a gate electrode on the gate insulating layer (planar top portion of gate 160 having gate insulating film 161 disposed adjacent first body region 150 and gate electrode 163 disposed on film 161; Fig. 3; paragraph [0055]); and
a second trench gate in the first body region (another trench gate 160 in first portion of body region 150; Fig. 3; paragraphs [0053]-[0054]).
Kim fails to disclose wherein a lowermost surface of the first body region is deeper in the drift region than a lowermost surface of the second body region; a planar gate between the adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates, the planar gate including a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the first gate insulating layer; and a second trench gate in the first body region connected to the planar gate.
However, the relative difference in the depth between the first and second body regions is not claimed and therefore would include very minor differences in depths which will occur during fabrication of the two regions given inherent error in manufacturing processes. Further, significant differences in depth between the regions is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower on-state resistance, improved switching performance, and enhanced breakdown voltage.
Kim, as modified, fails to disclose a planar gate between the adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates, the planar gate including a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the first gate insulating layer; and a second trench gate in the first body region connected to the planar gate.
However, Rahimo discloses a planar gate between the adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates (planar gate electrode 10 disposed between adjacent trench gate electrodes 11 and portions of planar gate electrode 10 do not overlap with trench gate electrodes 11; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]), the planar gate including a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the first gate insulating layer (planar gate electrode 10 having insulating layer 12 on upper surface of drift and base layers 4, 9 and electrode on insulating layer 12; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]); and a second trench gate in the first body region connected to the planar gate (second trench gate 11 in drift and base layers 4, 9 and connected to planar gate electrode; Fig. 3; paragraphs [0053]-[0054]).
Kim and Rahimo are both considered to be analogous to the claimed invention because they are in the same field of IGBTs. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teaching of Rahimo in order to potentially provide reduced on-state voltage drop and conduction losses, improved trade-off between on-state and turn-off losses, and enhanced reliability and breakdown voltage management.
Regarding claim 9, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 7. Kim further discloses wherein the second trench gate has a lowermost surface in the first body region (the other trench gate 160 has a lower concave surface that extends through the first body region 150; Fig. 3; paragraphs [0053]-[0054]).
Regarding claim 10, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 7. Kim fails to disclose wherein the second trench gate has a shallower depth than the first trench gates.
However, the relative difference in the depth between the gates is not claimed and therefore would include very minor differences in depths which will occur during fabrication of the two gates given inherent error in manufacturing processes. Further, significant differences in depth between the gates is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower turn-off losses, reduced gate charge, and improved on-state voltage drop.
Regarding claim 11, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 10. Kim fails to disclose wherein the second trench gate has a narrower width than the first trench gates.
However, the relative difference in the width between the gates is not claimed and therefore would include very minor differences in widths which will occur during fabrication of the two gates given inherent error in manufacturing processes. Further, significant differences in width between the gates is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower on-state voltage drop, enhanced breakdown voltage, and improved scalability.
Regarding claim 12, as best understood, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 7. Kim further discloses wherein the second trench gate comprises: a second gate insulating layer on an inner wall of a trench; and a second gate electrode on an inner wall of the second gate insulating layer and filling the trench, wherein the second trench gate electrode contacts the first gate electrode (planar top portion of gate 160 having gate insulating film 161 on inner wall of trench and gate electrode 163 disposed on film 161 and filling trench, where first body region 150 is floating; Fig. 3; paragraphs [0055]-[0056]).
Regarding claim 13, as best understood, Kim discloses an insulated gate bipolar transistor comprising:
a collector electrode (IGBT 1 having collector electrode 110; Fig. 3; paragraphs [0051]-[0052]);
a collector on the collector electrode (collector layer 120 disposed on collector electrode 110; Fig. 3; paragraph [0052]);
a drift region on the collector (drift region 140 on collector layer 120; Fig. 3; paragraph [0052]);
a plurality of first trench gates spaced apart from each other in the drift region (first and second trench gates 160 spaced apart in drift region 140; Fig. 3; paragraph [0054]);
a floating first body region between first adjacent ones of the first trench gates and in the drift region, in a floating region of the insulated gate bipolar transistor (first portion of body region 150 floating between first adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
a second body region between second adjacent ones of the first trench gates and in the drift region, in an active region of the insulated gate bipolar transistor (second portion of body region 150 in active region of IGBT 1 and between second adjacent trench gates 160 and in drift region 140; Fig. 3; paragraphs [0053]-[0054]); and
a planar gate including a gate insulating layer on the first body region and a gate electrode on the gate insulating layer (planar top portion of gate 160 having gate insulating film 161 disposed adjacent first body region 150 and gate electrode 163 disposed on film 161; Fig. 3; paragraph [0055]); and
a second trench gate in the first body region and spaced apart from the first adjacent ones of the first trench gates, and having a lowermost surface deeper than a lowermost surface of the first body region (another trench gate 160 spaced apart from first and second trench gates 160 in first portion of body region 150 and having lower concave surface that extends through the first body region 150 into the drift region 140; Fig. 3; paragraphs [0053]-[0054]).
Kim fails to disclose a planar gate between the first adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates, the planar gate including a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the gate insulating layer; and a second trench gate connected to the planar gate.
However, Rahimo discloses a planar gate between the first adjacent ones of the first trench gates and not overlapping with the first adjacent ones of the first trench gates (planar gate electrode 10 disposed between adjacent trench gate electrodes 11 and portions of planar gate electrode 10 do not overlap with trench gate electrodes 11; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]), the planar gate including a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the gate insulating layer (planar gate electrode 10 having insulating layer 12 on upper surface of drift and base layers 4, 9 and electrode on insulating layer 12; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]); and a second trench gate connected to the planar gate (second trench gate 11 in drift and base layers 4, 9 and connected to planar gate electrode; Fig. 3; paragraphs [0053]-[0054]).
Kim and Rahimo are both considered to be analogous to the claimed invention because they are in the same field of IGBTs. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teaching of Rahimo in order to potentially provide reduced on-state voltage drop and conduction losses, improved trade-off between on-state and turn-off losses, and enhanced reliability and breakdown voltage management.
Regarding claim 14, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 13. Kim fails to disclose wherein the second trench gate has a narrower width and a smaller vertical length than the first trench gates.
However, the relative difference in the width and depth between the gates is not claimed and therefore would include very minor differences in widths and depths which will occur during fabrication of the two gates given inherent error in manufacturing processes. Further, significant differences in width and depth between the gates is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower on-state voltage drop, enhanced breakdown voltage, and improved scalability.
Regarding claim 15, Kim in view of Rahimo discloses the insulated gate bipolar transistor of claim 14. Kim further discloses wherein the second body region has a lowermost surface at substantially a same depth as a lowermost surface of the first body region (first and second body region 150 having same depth into IGBT 1; Fig. 3).
Regarding claim 16, as best understood, Kim discloses a method of manufacturing an insulated gate bipolar transistor, the method comprising:
forming a drift region on a collector (method of forming IGBT 1 with drift region 140 on collector layer 120; Fig. 3; paragraph [0052]);
forming a floating first body region in the drift region in a floating region of the insulated gate bipolar transistor (first portion of body region 150 floating in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
forming a plurality of first trench gates spaced apart from each other in the drift region (first and second trench gates 160 spaced apart in drift region 140; Fig. 3; paragraph [0054]);
forming a planar gate including a gate insulating layer on the first body region and a gate electrode on the gate insulating layer (planar top portion of gate 160 having gate insulating film 161 disposed adjacent first body region 150 and gate electrode 163 disposed on film 161; Fig. 3; paragraph [0055]);
forming a second body region in the drift region in an active region of the insulated gate bipolar transistor (second portion of body region 150 in active region of IGBT 1 in drift region 140; Fig. 3; paragraphs [0053]-[0054]);
forming an emitter in the second body region (second portion of body region 150 having emitter 181; Fig. 3; paragraph [0056]);
forming an interlayer insulating layer on the first body region and the second body region and covering the planar gate; and
forming an emitter electrode on the interlayer insulating layer (interlayer insulating film 170 disposed over planar top portion of gate 160 and first and second portions of body region 150, where emitter electrode 190 is disposed over film 170 and first portion of body region 150 is floating; Fig. 3; paragraph [0056]).
Kim fails to disclose forming a planar gate on the first body region, wherein the planar gate includes a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the gate insulating layer, and the planar gate does not overlap with the first trench gates.
However, Rahimo discloses forming a planar gate on the first body region, wherein the planar gate includes a first gate insulating layer on an uppermost surface of the first body region and a first gate electrode on the gate insulating layer (planar gate electrode 10 having insulating layer 12 on upper surface of drift and base layers 4, 9 and electrode on insulating layer 12; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]), and the planar gate does not overlap with the first trench gates (planar gate electrode 10 disposed between adjacent trench gate electrodes 11 and portions of planar gate electrode 10 do not overlap with trench gate electrodes 11; Figs. 7 and 10; paragraphs [0088]-[0089], [0106]).
Kim and Rahimo are both considered to be analogous to the claimed invention because they are in the same field of IGBTs. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teaching of Rahimo in order to potentially provide reduced on-state voltage drop and conduction losses, improved trade-off between on-state and turn-off losses, and enhanced reliability and breakdown voltage management.
Regarding claim 17, Kim in view of Rahimo discloses the method of claim 16. Kim further discloses wherein forming the plurality of first trench gates comprises: forming a plurality of first trenches having a first depth in the drift region (trenches of first and second trench gates 160 have a depth in drift region 140; Fig. 3); forming an insulating layer in the first trenches and on the first body region (gate insulating film 161 disposed in trenches and along first portion of body region 150; Fig. 3); and forming a polysilicon layer on the insulating layer to form the first trench gates (gate electrode of trench gates 160 may comprise polysilicon disposed upon film 161; Fig. 3; paragraph [0055]), wherein the insulating layer forms the first gate insulating layer and a second gate insulating layer for the first trench gates (gate insulating film 161 serves as gate insulating layers for trench gates 160; Fig. 3).
Regarding claim 18, Kim in view of Rahimo discloses the method of claim 17. Kim further discloses further comprising forming a second trench having a second depth between a pair of the first trenches and in the first body region, forming the insulating layer in the second trench, and forming the polysilicon layer in the second trench (trench of another trench gate 160 having a depth disposed through first portion of body region 150 and between first and second trench gates 160, where polysilicon is used as gate electrode in each trench gate 160; Fig. 3; paragraph [0055]).
Kim fails to disclose wherein the second depth is shallower than the first depth.
However, the relative difference in the depth between the gates is not claimed and therefore would include very minor differences in depths which will occur during fabrication of the two gates given inherent error in manufacturing processes. Further, significant differences in depth between the gates is a mere matter of design choice for known benefits.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in this manner in order to potentially provide lower turn-off losses, reduced gate charge, and improved on-state voltage drop.
Regarding claim 19, Kim in view of Rahimo discloses the method of claim 17. Kim further discloses wherein forming the emitter electrode on the interlayer insulating layer comprises: forming a contact hole in the interlayer insulating layer in the active region (opening formed within interlayer insulating film 170 in active region of IGBT 1; Fig. 3); forming a body contact in the second body region through the contact hole (body contact 183 in second portion of body region 150 through opening; Fig. 3; paragraphs [0054], [0056]-[0058]); and forming a conductive layer in the contact hole and on the interlayer insulating layer (emitter electrode 190 comprises a conductive layer disposed within opening of film 170; Fig. 3; paragraph [0056]).
Regarding claim 20, Kim in view of Rahimo discloses the method of claim 17. Kim further discloses wherein forming the planar gate comprises etching the polysilicon layer on the insulating layer (planar top portion of another gate 160 formed by chemical removal of excess polysilicon gate electrode material; Figs. 10-11; paragraph [0078]).
Regarding claim 21, Kim in view of Rahimo discloses the method of claim 1. Kim further discloses further comprising a gate to collector parasitic capacitance, wherein the first trench gates and the collector have a first trench gate to collector parasitic capacitance, the planar gate and the collector have a planar gate to collector parasitic capacitance, and the gate to collector parasitic capacitance is a sum of the first trench gate to collector parasitic capacitance and the planar gate to collector parasitic capacitance (trench gates 160 inherently comprise parasitic capacitance values that sum to a gate-to-collector parasitic capacitance value; Fig. 3; paragraph [0051]).
Regarding claim 22, Kim in view of Rahimo discloses the method of claim 1. Kim further discloses wherein the floating first body region does not contact a lowermost surface of the first adjacent ones of the first trench gates (floating first portion of body region 150 does not contact lowest surface of trench gates 160; Fig. 3; paragraphs [0053]-[0054]).
Regarding claim 23, Kim in view of Rahimo discloses the method of claim 7. Kim further discloses further comprising a gate to collector parasitic capacitance, wherein the first trench gates and the collector have a first trench gate to collector parasitic capacitance, the planar gate and the collector have a planar gate to collector parasitic capacitance, and the gate to collector parasitic capacitance is a sum of the first trench gate to collector parasitic capacitance and the planar gate to collector parasitic capacitance (trench gates 160 inherently comprise parasitic capacitance values that sum to a gate-to-collector parasitic capacitance value; Fig. 3; paragraph [0051]).
Response to Arguments
Applicant’s arguments submitted January 8, 2026 have been fully considered. Specifically, Applicant substantively amended the independent claims, submitted corresponding arguments, and added new claims 21-23. Examiner thanks Applicant for providing a thorough analysis of both Kim and Rahimo as well as list of technical advantages of some features of the claim language. However, Examiner disagrees with Applicant’s assertion that the combination of Kim and Rahimo does not disclose amended claims 1, 7, 13 and 16. As outlined above, Kim discloses and suggests a portion of the amended claim language and Rahimo discloses the remaining amended claim language. While Applicant asserts that Rahimo does not disclose “the planar gate does not overlap with the first trench gates”, Examiner must use the broadest reasonable interpretation of this limitation which is disclosed by Rahimo in that portions of the planar gate electrode 10 do not overlap with trench gates 160.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818