DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 11, 2025, has been entered.
Claims 1, 3-4, and 6-7 are pending in this office action and presented for examination. Claims 1, 3-4, and 6-7 are newly amended by the response received November 11, 2025.
Claim Objections
Claims 1, 3-4, and 6-7 are objected to because of the following informalities. Appropriate correction is required.
In claim 1, line 17, the acronym “PC” should be expanded.
Claims 3-4 and 6 are objected to for failing to alleviate the objection of claim 1 above.
In claim 7, line 14, the acronym “PC” should be expanded.
In claim 7, line 27, “invalidate” should be “invalidating” for grammatical clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “register a stride width in a second entry in the prefetch queue, the stride width being calculated by subtracting the predicted address that is registered in the first entry from the request address of a second memory access instruction with respect to which a PC hit occurs” in lines 15-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for registering a stride width in “a second entry” in the prefetch queue, the stride width being calculated by subtracting the predicted address that is registered in “the first entry” from the request address of a second memory access instruction with respect to which a PC hit occurs. Similarly, see the functionality associated with “the second entry” in claim 1, line 21, and claim 1, lines 21-22. Similarly, see the functionality associated with “the respective entry” in claim 1, line 36; claim 3, line 3; claim 3, line 6; claim 3, line 7; claim 3, line 10; and claim 3, lines 11-12.
Claim 1 recites the limitation “the PC hit occurring with a value of a program counter of a subject memory access instruction matching a value of a program counter registered in at least one entry in the prefetch queue” in lines 18-20. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for a PC hit occurring with a value of a program counter of a subject memory access instruction matching a value of a program counter registered in “at least one” entry in the prefetch queue.
Claim 1 recites the limitation “for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, update sequentially a respective predicted address, in each of another entry in the prefetch queue respectively corresponding to each of the plurality of third memory access instructions, with an address calculated by adding the calculated stride width, respectively, to each of request addresses of the plurality of third memory access instructions” in lines 24-28. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 6 and FIG. 12) does not appear to provide support for, for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, update sequentially a respective predicted address, in “each of another entry” in the prefetch queue respectively corresponding to each of the plurality of third memory access instructions, with an address calculated by adding the calculated stride width, respectively, to each of request addresses of the plurality of third memory access instructions.
Claim 1 recites the limitation “detect occurrence of a stride access based on request addresses of a plurality of memory access instructions having the PC hit and the calculated stride width, by comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address corresponding respectively to each of the plurality of third memory access instructions that is registered in the respective entry” in lines 32-36. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 6 and FIG. 12) does not appear to provide support for a comparison of a request address of an earliest memory access instruction of the plurality of third memory access instructions with an updated predicted address corresponding to a third memory access instruction that is registered in the respective entry.
Claims 3-4 and 6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 3 recites the limitation “increase a confidence counter in the respective entry for a respective one of the third memory access instructions when a request address of a memory access instruction among the third memory access instructions and the respective predicted address that is updated and registered in the respective entry match” in lines 3-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 6 and FIG. 12) does not appear to provide support for increasing a confidence counter in a respective entry when a request address and an updated predicted address in that respective entry match.
Claim 3 recites the limitation “reduce the confidence counter in the respective entry for a respective one of the third memory access instructions when the request address of the memory access instruction among the third memory access instructions and the respective predicted address that is updated and registered in the respective entry do not match” in lines 7-10. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 8 and FIG. 12) does not appear to provide support for reducing a confidence counter in a respective entry when a request address and an updated predicted address in that respective entry do not match.
Claim 7 recites the limitation “registering a stride width in a second entry in the prefetch queue, the stride width being calculated by subtracting the predicted address that is registered in the entry from the request address of a second memory access instruction with respect to which a PC hit occurs” in lines 12-14. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for registering a stride width in “a second entry” in the prefetch queue, the stride width being calculated by subtracting the predicted address that is registered in “the first entry” from the request address of a second memory access instruction with respect to which a PC hit occurs. Similarly, see the functionality associated with “the second entry” in claim 7, line 18, and claim 7, lines 18-19. Similarly, see the functionality associated with “the respective entry” in claim 7, line 33.
Claim 7 recites the limitation “the PC hit occurring with a value of a program counter of a subject memory access instruction matching a value of a program counter registered in at least one entry in the prefetch queue” in lines 15-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 12) does not appear to provide support for a PC hit occurring with a value of a program counter of a subject memory access instruction matching a value of a program counter registered in “at least one” entry in the prefetch queue.
Claim 7 recites the limitation “for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, updating sequentially a respective predicted address, in each of another entry in the prefetch queue respectively corresponding to each of the plurality of third memory access instructions, with an address calculated by adding the calculated stride width, respectively, to each of request addresses of the plurality of third memory access instructions” in lines 21-25. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 6 and FIG. 12) does not appear to provide support for, for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, update sequentially a respective predicted address, in “each of another entry” in the prefetch queue respectively corresponding to each of the plurality of third memory access instructions, with an address calculated by adding the calculated stride width, respectively, to each of request addresses of the plurality of third memory access instructions.
Claim 7 recites the limitation “detecting occurrence of a stride access based on request addresses of a plurality of memory access instructions having the PC hit and the calculated stride width, by comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address corresponding respectively to each of the plurality of third memory access instructions that is registered in the respective entry” in lines 29-33. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 6 and FIG. 12) does not appear to provide support for a comparison of a request address of an earliest memory access instruction of the plurality of third memory access instructions with an updated predicted address corresponding to a third memory access instruction that is registered in the respective entry.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a prefetch queue” in line 11. However, it is indefinite as to whether this prefetch queue is the same as, or different from, “a prefetch queue” as recited in claim 1, line 2. If the same, antecedent basis language should be used for clarity.
Claim 1 recites the limitation “the prefetch queue” in line 15. However, it is indefinite as to whether the antecedent basis for this limitation is “a prefetch queue” in claim 1, line 2, or “a prefetch queue” in claim 1, line 11. Note that this limitation is also recited in claim 1, line 20; claim 1, line 26; claim 1, line 29; claim 1, line 30; claim 6, line 2; and claim 6, lines 5-6.
Claim 1 recites the limitation “the request address of a second memory access instruction with respect to which a PC hit occurs” in lines 16-17. However, there is insufficient antecedent basis for this limitation in the claims. Note that the similar limitation “the request address of the second memory access instruction” is recited in claim 1, lines 22-23.
Claim 1 recites the limitation “a subject memory access instruction” in line 19. However, it is indefinite as to whether this instruction is the same as, or different from, “a second memory access instruction” as recited in claim 1, line 17.
Claim 1 recites the limitation “a value of a program counter registered in at least one entry in the prefetch queue” in lines 19-20. However, it is indefinite as to whether this value is the same as, or different from, the value of the limitation “register, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 1, lines 11-12.
Claim 1 recites the limitation “a program counter registered in at least one entry in the prefetch queue” in lines 19-20. However, it is indefinite as to whether this program counter is the same as, or different from, the program counter of the limitation “register, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 1, lines 11-12.
Claim 1 recites the limitation “at least one entry in the prefetch queue” in line 20. However, it is indefinite as to whether this at least one entry is the same as, or different from, the entry of the limitation “register, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 1, lines 11-12.
Claim 1 recites the limitation “the PC hit” in line 24. However, it is indefinite as to whether this PC hit has antecedent basis back to “a PC hit” of claim 1, line 17 (which appears to be in the context of a second memory access instruction and a first entry) or “PC hit” of claim 1, line 18 (which appears to be in the context of a subject memory access instruction and at least one entry) or another instance of a PC hit.
Claim 1 recites the limitation “detect occurrence of a stride access based on request addresses of a plurality of memory access instructions having the PC hit and the calculated stride width, by comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address corresponding respectively to each of the plurality of third memory access instructions that is registered in the respective entry” in lines 32-36. However, it is indefinite as to whether “a plurality of memory access instructions having the PC hit” in the limitation above is the same as, or different from, “a plurality of third memory access instructions having the PC hit” of, for example, claim 1, line 24, in view of the context of the remaining language in the limitation above.
Claims 3-4 and 6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 3 recites the limitation “increase a confidence counter in the respective entry for a respective one of the third memory access instructions when a request address of a memory access instruction among the third memory access instructions and the respective predicted address that is updated and registered in the respective entry match” in lines 3-6. However, it is indefinite as to whether “a memory access instruction” in claim 3, line 4, is the same as, or different from, “a respective one of the third memory access instructions” in claim 3, lines 3-4.
Claim 3 recites the limitation “reduce the confidence counter in the respective entry for a respective one of the third memory access instructions when the request address of the memory access instruction among the third memory access instructions and the respective predicted address that is updated and registered in the respective entry do not match” in lines 7-10. However, it is indefinite as to whether “the memory access instruction” in claim 3, line 8, is the same as, or different from, “a respective one of the third memory access instructions” in claim 3, lines 7-8.
Claim 3 recites the limitation “a respective one of the third memory access instructions” in lines 7-8. However, it is indefinite as to whether this third memory access instruction is the same as, or different from, “a respective one of the third memory access instructions” as recited in claim 3, lines 3-4.
Claim 4 recites the limitation “a memory access instruction among the plurality of memory access instructions having the PC hit” in lines 4-6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether this memory access instruction is the same as, or different from, “a subject memory access instruction” of the limitation “the PC hit occurring with a value of a program counter of a subject memory access instruction” in claim 1, lines 18-19, and/or “a second memory access instruction” of the limitation “a second memory access instruction with respect to which a PC hit occurs” in claim 1, line 17.
Claim 6 recites the limitation “frequent address misses” in line 6. However, the claim does not particularly point out and distinctly define the metes and bounds of the subject matter to be protected by the patent grant, because it would not be clear to a hypothetical person possessing the ordinary level of skill in the pertinent art whether a particular quantity of address misses at particular times would be considered to be "frequent" or not. Examiner notes that the disclosure does not explicitly or implicitly provide definite criteria by which to determine whether a particular quantity of address misses at particular times would be considered to be "frequent" or not. Consequently, the scope of the claim is unclear.
Claim 6 recites the limitation “low probability of being used for stride prefetching” in line 6. However, the claim does not particularly point out and distinctly define the metes and bounds of the subject matter to be protected by the patent grant, because it would not be clear to a hypothetical person possessing the ordinary level of skill in the pertinent art whether a particular probability of being used for stride prefetching would be considered to be “low” or not. Examiner notes that the disclosure does not explicitly or implicitly provide definite criteria by which to determine whether a probability of being used for stride prefetching would be considered to be “low” or not. Consequently, the scope of the claim is unclear.
Claim 7 recites the limitation “the request address of a second memory access instruction with respect to which a PC hit occurs” in lines 13-14. However, there is insufficient antecedent basis for this limitation in the claims. Note that the similar limitation “the request address of the second memory access instruction” is recited in claim 7, lines 19-20.
Claim 7 recites the limitation “a subject memory access instruction” in line 16. However, it is indefinite as to whether this instruction is the same as, or different from, “a second memory access instruction” as recited in claim 7, line 14.
Claim 7 recites the limitation “a value of a program counter registered in at least one entry in the prefetch queue” in lines 16-17. However, it is indefinite as to whether this value is the same as, or different from, the value of the limitation “registering, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 7, lines 8-9.
Claim 7 recites the limitation “a program counter registered in at least one entry in the prefetch queue” in lines 16-17. However, it is indefinite as to whether this program counter is the same as, or different from, the program counter of the limitation “registering, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 7, lines 8-9.
Claim 7 recites the limitation “at least one entry in the prefetch queue” in line 17. However, it is indefinite as to whether this at least one entry is the same as, or different from, the entry of the limitation “registering, in a prefetch queue, a first entry in which a value of a program counter of a first memory access instruction” in claim 7, lines 8-9.
Claim 7 recites the limitation “the PC hit” in line 21. However, it is indefinite as to whether this PC hit has antecedent basis back to “a PC hit” of claim 7, line 14 (which appears to be in the context of a second memory access instruction and an entry) or “PC hit” of claim 7, line 15 (which appears to be in the context of a subject memory access instruction and at least one entry) or another instance of a PC hit.
Claim 7 recites the limitation “detecting occurrence of a stride access based on request addresses of a plurality of memory access instructions having the PC hit and the calculated stride width by comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address corresponding respectively to each of the plurality of third memory access instructions that is registered in the respective entry” in lines 29-33. However, it is indefinite as to whether “a plurality of memory access instructions having the PC hit” in the limitation above is the same as, or different from, “a plurality of third memory access instructions having the PC hit” of, for example, claim 7, line 21, in view of the context of the remaining language in the limitation above.
Claim 7 recites the limitation “the predicted address that is registered in the entry” in line 13. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 7 recites the limitation “the entry” in line 13. However, there is insufficient antecedent basis for this limitation in the claims.
Response to Arguments
Applicant on page 8 argues: “By this Amendment, the claims are amended to clarify features. No new matter was added. The rejections under 35 USC §§ 112(a) and (b) are now moot.”
The previously presented rejections of the claims under 35 U.S.C. §112(a) and 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, the amendments to the claims introduce additional issues under 35 U.S.C. §112(a) and 35 U.S.C. §112(b) — see the Claim Rejections - 35 USC § 112 section above.
Conclusion
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183