DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-4, and 6-7 are pending in this office action and presented for examination. Claims 1, 3-4, and 6-7 are newly amended by the response received April 14, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “after registering the stride width in the entry in the prefetch queue, update the predicted address in the entry in the prefetch queue with the request address of the second memory access instruction to which the calculated stride width is added” in lines 17-20. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g. paragraph [0045], paragraph [0065], and FIG. 6) does not appear to provide support for updating the predicted address in the entry in the prefetch queue with the request address of the second memory access instruction, and adding the calculated stride width to the aforementioned request address of the second memory access instruction in the entry in the prefetch queue.
Claim 1 recites the limitation “for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, update the predicted address in the entry in the prefetch queue with a respective one of request addresses of the plurality of third memory access instructions to which the calculated stride width is added” in lines 21-26. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g. paragraph [0049], paragraph [0066], and FIG. 6) does not appear to provide support for updating the predicted address in the entry in the prefetch queue with a request address of a third memory access instruction, and adding the calculated stride width to the aforementioned request address of the third memory access instruction in the entry in the prefetch queue.
Claims 3-4 and 6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 3 recites the limitation “increase a confidence counter in the entry in the prefetch queue for a respective one of the third memory access instructions when the request address of the respective one of the third memory access instructions and the predicted address that is previously registered in the entry in the prefetch queue match” in lines 3-7. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 4) does not appear to provide support for increasing a confidence counter in the entry in the prefetch queue for a third memory access instruction when the request address of the third memory access instruction and the predicted address that is previously registered in the entry in the prefetch queue (i.e., the predicted address of claim 1, lines 7-8) match.
Claim 3 recites the limitation “reduce the confidence counter in the entry in the prefetch queue for the respective one of the third memory access instructions when the request address of the respective one of the third memory access instructions and the predicted address that is previously registered in the entry in the prefetch queue do not match” in lines 8-12. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 4) does not appear to provide support for reducing a confidence counter in the entry in the prefetch queue for a third memory access instruction when the request address of the third memory access instruction and the predicted address that is previously registered in the entry in the prefetch queue (i.e., the predicted address of claim 1, lines 7-8) do not match.
Claim 7 recites the limitation “after registering the stride width in the entry in the prefetch queue, updating the predicted address in the entry in the prefetch queue with the request address of the second memory access instruction to which the calculated stride width is added” in lines 14-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g. paragraph [0045], paragraph [0065], and FIG. 6) does not appear to provide support for updating the predicted address in the entry in the prefetch queue with the request address of the second memory access instruction, and adding the calculated stride width to the aforementioned request address of the second memory access instruction in the entry in the prefetch queue.
Claim 7 recites the limitation “for each of a plurality of third memory access instructions having the PC hit following the second memory access instruction, updating the predicted address in the entry in the prefetch queue with a respective one of request addresses of the plurality of third memory access instructions to which the calculated stride width is added” in lines 18-23. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g. paragraph [0049], paragraph [0066], and FIG. 6) does not appear to provide support for updating the predicted address in the entry in the prefetch queue with a request address of a third memory access instruction, and adding the calculated stride width to the aforementioned request address of the third memory access instruction in the entry in the prefetch queue.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address that is previously registered in the entry in the prefetch queue” in lines 31-34. However, the metes and bounds of this limitation are indefinite. For example, the antecedent basis of “the updated predicted address that is previously registered in the entry in the prefetch queue” is unclear. For example, for a second instance of a third memory access instruction, there appears to be two potential sources of antecedent basis for “the updated predicted address that is previously registered in the entry in the prefetch queue” — an updated predicted address of claim 1, lines 17-18, and an updated predicted address of claim 1, line 22, associated with a first instance of a third memory access instruction. For example, for a third instance of a third memory access instruction, there appears to be three potential sources of antecedent basis for “the updated predicted address that is previously registered in the entry in the prefetch queue” — an updated predicted address of claim 1, lines 17-18; an updated predicted address of claim 1, line 22, associated with a first instance of a third memory access instruction; and an updated predicted address of claim 1, line 22, associated with a second instance of a third memory access instruction. Examiner further notes that the recitation of the “updated” predicted address in claim 1, lines 32-33, makes it unclear as to whether the recitation of, for example, “the predicted address” (sans “updated”) in claim 1, line 22, is particularly referring to “a predicted address” in claim 1, line 8. Note that “the predicted address” (sans “updated”) is recited in claim 3, lines 5-6; and claim 3, lines 10-11.
Claims 3-4 and 6 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 7 recites the limitation “request addresses of the plurality of third memory access instructions” in lines 27-28. However, it is indefinite as to whether these request addresses are the same as, or different from, “request addresses of the plurality of third memory access instructions” as recited in claim 7, lines 22-23.
Claim 7 recites the limitation “comparing each of the request addresses of the plurality of third memory access instructions with the updated predicted address that is previously registered in the entry in the prefetch queue” in lines 28-31. However, the metes and bounds of this limitation are indefinite. For example, the antecedent basis of “the updated predicted address that is previously registered in the entry in the prefetch queue” is unclear. For example, for a second instance of a third memory access instruction, there appears to be two potential sources of antecedent basis for “the updated predicted address that is previously registered in the entry in the prefetch queue” — an updated predicted address of claim 7, line 15, and an updated predicted address of claim 7, line 19, associated with a first instance of a third memory access instruction. For example, for a third instance of a third memory access instruction, there appears to be three potential sources of antecedent basis for “the updated predicted address that is previously registered in the entry in the prefetch queue” — an updated predicted address of claim 7, line 15; an updated predicted address of claim 7, line 19, associated with a first instance of a third memory access instruction; and an updated predicted address of claim 7, line 19, associated with a second instance of a third memory access instruction. Examiner further notes that the recitation of the “updated” predicted address in claim 7, lines 29-30, makes it unclear as to whether the recitation of, for example, “the predicted address” (sans “updated”) in claim 7, line 19, is particularly referring to “a predicted address” in claim 7, line 5.
Response to Arguments
Applicant on page 7 argues: “Claims 1, 3-4, and 6-7 are objected to because of minor informalities in claims 1 and 7. The Examiner's suggested corrections were much appreciated. Claims 1 and 7 are amended accordingly.”
In view of the aforementioned amendments, the previously presented claim objections are withdrawn.
Applicant on page 7 argues: ‘Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. § 112(a) for lack of written description support. The Examiner's explanations during the interview were much appreciated, including how most of these rejections involved a broad interpretation of the claimed various "entries" (first, second, third) having the PC hit as implying multiple different physical entries in the prefetch queue. The claims are amended above to preclude such an interpretation. Accordingly, these rejections are now moot. As for claim 6, a predetermined quantity of address misses is supported, for example, in para. 0169, and a threshold probability of being used for stride prefetching is supported, for example, in para. 0170 of the present specification as originally filed. Claims 1, 3-4, and 6-7 are rejected under 35 U.S.C. § 112(b) as being indefinite. These rejections are now moot in view of the above claim amendments.’
In view of the aforementioned amendments, the previously presented rejections under 35 U.S.C. § 112(a) and 35 U.S.C. § 112(b) are withdrawn. However, the newly amended limitations appear to catalyze various additional issues under 35 U.S.C. § 112(a) and 35 U.S.C. § 112(b) — see the Claim Rejections - 35 USC § 112 section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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