DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot in view of applicant’s amendments. Since the invention of Lin is in a flipped orientation. Bottom surfaces are shown to be on the top. Top surfaces are shown to be on the bottom.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,6-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120187568 A1; Lin) in view of Kuo et al. (US 20210375708 A1: Kuo).
Regarding claim 1, Lin discloses an electronic device, comprising a substrate (Fig. 5S, 172; ¶56) comprising: a dielectric layer (Fig. 5S, 238; ¶73) comprising a dielectric layer top side, a dielectric layer bottom side, a dielectric layer lateral side between the dielectric layer top side and the dielectric layer bottom side, and a dielectric layer aperture (location of 240 pattern) that pass through the dielectric layer from the dielectric layer top side to the dielectric layer bottom side; a conductive pattern on (Fig. 5S, 240; ¶73)…, wherein the conductive pattern extends into the dielectric layer aperture toward the dielectric layer top side;… wherein the conductive pattern extends into the dielectric layer aperture toward the dielectric layer top side; an external interconnect first structure (Fig. 5S, 244; ¶76) comprising an external interconnect first structure top side coupled (electrically) to the conductive pattern; and a substrate encapsulant (Fig. 5S, 242; ¶75) that surrounds and contacts the dielectric layer lateral side, a lateral side of the conductive pattern, and a lateral side of the external interconnect first structure; and a semiconductor component (Fig. 5S, 124; ¶65) comprising a component bottom side coupled to the dielectric layer top (indirectly through 172) side and an interconnection structure (Fig. 5S, 144; ¶65) electrically coupled to the conductive pattern.. ; and a component encapsulant (Fig. 5S, 212; ¶67) that laterally surrounds the semiconductor component (Fig. 5S, 124; ¶65), wherein the component encapsulant comprises a component encapsulant bottom side that contacts a top side of the substrate encapsulant.
Since the device of Lin is flipped the top is oriented on the bottom; the bottom is oriented on the top.
Lin is silent on using a seed layer.
Kuo discloses a device in a flipped orientation from Lin where the seed layer, a seed layer (Fig. 15B, between RDL via V1 and chip contact 138t; ¶143) on the dielectric layer bottom side, wherein the seed layer extends into the dielectric layer aperture toward the dielectric layer top side; a conductive pattern (Fig. 15B, CL1; ¶143) on the seed layer,
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a seed layer with the conductive patterns for aiding in connecting the conductor to other conductive layers.
Regarding claim 2, Lin discloses the electronic device of claim 1, wherein the dielectric layer (Fig. 5S, 238; ¶73) comprises a photo-definable dry film.
Photo-definable is interpreted to mean that the layer may be patterned using light.
Regarding claim 3, Lin discloses the electronic device of claim 1, wherein the dielectric layer comprises a dry film of dielectric material that is not photo-definable. (Fig. 5S, 238; ¶73)
Applicant uses lasers (light) to pattern both definable and not photo-definable. (¶58 & 61) It is unclear what applicant means by not photo-definable in light of the written description. Laminating layers does not cause a material to become not photo-definable unless layers between the target layer and light source change the composition of the layer to make it resistant to a light source.
Regarding claim 6, Lin discloses the electronic device of claim 1, wherein the component encapsulant (Fig. 5S, 212; ¶67) contacts a component (Fig. 5S, 124; ¶67) lateral side of the semiconductor component.
Since the device of Lin is flipped the top is oriented on the bottom; the bottom is oriented on the top.
Regarding claim 7, Lin discloses the electronic device of claim 1, wherein the component encapsulant (Fig. 5S, 212; ¶67) contacts a component (Fig. 5S, 124; ¶67) top side and a component lateral side of the semiconductor component.
Since the device of Lin is flipped the top is oriented on the bottom; the bottom is oriented on the top.
Regarding claim 8, Lin discloses the electronic device of claim 1, wherein: the conductive pattern (Fig. 5S, 240; ¶74) comprises one or more electroplated conductive layers; and the external interconnect first structure (Fig. 5S, 244; ¶76) comprises one or more electroplated conductive layers.
Regarding claim 9, Lin discloses the electronic device of claim 1, wherein the seed layer (Fig. 15B, between RDL via V1 and contact 138t; ¶143 Kuo) contacts the interconnection structure (Fig. 15B, electric contact to 132; ¶61 Kuo) of the semiconductor component.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a seed layer with the conductive patterns for aiding in connecting the conductor to other conductive layers.
Regarding claim 10, Lin discloses the electronic device of claim 1, wherein: a width of the dielectric layer (Fig. 5S, 238; ¶73) between opposite dielectric lateral sides is greater than a width of the semiconductor component (Fig. 5S, 124; ¶67) between corresponding component lateral sides; and the width of the dielectric layer between the opposite dielectric lateral sides is less than a width of the substrate (Fig. 5S, 172; ¶67) between corresponding substrate lateral sides.
Regarding claim 11, Lin discloses the electronic device of claim 1, wherein the substrate (Fig. 5S, 172; ¶56) lacks a seed layer between the conductive pattern (Fig. 5S, 240; ¶74) and the external interconnect first structure. (Fig. 5S, 244; ¶76)
Regarding claim 12, Lin discloses the electronic device of claim 1, comprising: an external interconnect second structure (Fig. 5S,ball 244; ¶76) coupled to a bottom side of the external interconnect first structure (Fig. 5S, not shown UBM under 244; ¶76); and wherein the substrate encapsulant (Fig. 5S, 242; ¶75) laterally surrounds at least a portion of a lateral side of the external interconnect second structure.
Regarding claim 13, Lin discloses the electronic device of claim 12, wherein: the external interconnect first structure comprises (Fig. 5S, 244; ¶76 UBM comprises pillar under balls .A pillar is a stud) a conductive stud; and the external interconnect second structure comprises a solder ball. (Fig. 5S,ball 244; ¶76)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120187568 A1; Lin) in view of Kuo et al. (US 20210375708 A1: Kuo) and further in view of Hsieh et al. (US 4708943 A; Hsieh).
Regarding claim 4, Lin discloses the electronic device of claim 1, but is silent on wherein the dielectric layer has a loss tangent of 0.015 or less.
Lin discloses the insulating layer 238 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
In the art to achieve a desired loss tangent layers such as Si3N4 are laminated.
Hsieh discloses silicon nitride with a loss tangent from about 0.002 to about 0.02. (Column 1 lines 54-59)
The claimed loss tangent of 0.015 or less represents a range covered by Hsieh.
Therefore, while, Hsieh does not expressly teaches the range of 0.015 or less some of its value ” about 0.002 to about 0.02” fall within the claim range of 0.015 or less, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “about 0.002 to about 0.02”, as disclosed in prior art, to arrive at the recited limitation for the benefit of dielectric layer integrity in high temperature devices.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120187568 A1; Lin) in view of Kuo et al. (US 20210375708 A1: Kuo) and further in view of Strothmann et al. (US 20150243575 A1; Strothmann).
Regarding claim 5, Lin discloses the electronic device of claim 1, but is silent on wherein a thickness of the dielectric layer between the dielectric layer top side and the dielectric layer bottom side is greater than 20 pm.
Strothmann discloses a similar device with an analogous dielectric layer (Fig. 1, 170; ¶58) that is one or more layers, and includes a thickness of 7-11 mu. This is interpreted to mean dielectric layer 170 comprises three layers each with a thickness of 7-11mu.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to have a thickness greater than 20mu to accommodate high temperatures, high density, high speed functioning devices.
Allowable Subject Matter
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Cited art (US 20120187568 A1; Lin) discloses electroplating the conductive layer and external interconnect but does not have a seed layer. US-20220077077-A1 discloses electroplating multiple conductive layer buy passing current through a seed layer. CN-112542449-A discloses forming a TIV by running current through a seed layer. CN-111863601-A uses a second seed layer to grow an external conductor. The relative art does not disclose plating a conductive external layer by running a current through a seed layer
Regarding claim 14, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and electroplating an external interconnect first structure on the conductive pattern by applying current to the seed layer.”, as recited in Claim 14, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899