DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of Group- I ( claims 1-14 ) in the reply filed on 12/10 /2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 -14 are rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US PGpub : 2021 / 0020779 A1 ), herein after Lian , in view of know arts like Lian and Blanchard et al. (US PGpub : 2017 / 0069727 A1 ), herein after Blanchard or Amethystna et al. (US PGpub : 2024 / 0006529 A1 ), herein after Amethystna . Regarding claim 1 , Lian teaches a semiconductor device comprising: a semiconductor substrate (as shown in picture) ; a well resistor (20) in the semiconductor substrate; a field plate (60B) above the well resistor; and an insulator (60A) between the well resistor and the field plate. Lian does not explicitly teach the well resistor. . However, Lian teaches well resistor (the interpretation is that a well which flows current within can be a well resistor. Since current has to be flown from one terminal of the well to another terminal of the well in order for the device to function, the well 20 is considered well resistor) . This is also taught in FIG. 22 of Blanchard where p-well 54 is a conductive well . With reference to FIG. 4 in Amethystna , well 22 in considered well resistor as current flows from one terminal to the other. Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Lian ’ s semiconductor device with other teaching from Lian or Blanchard or Amethystna so that device characteristics like breakdown voltage can be improved . Regarding claim 2 , Lian (in view of Lian or Amethystna ) teaches t he semiconductor device of claim 1, wherein: the well resistor (20) includes a first terminal and a second terminal (first terminal on the right and second terminal is on the left in Lian ) and the field plate is conductively connected to the first terminal or the second terminal (field plate 60B is coupled to right portion of the terminal). In Amethystna , First terminal is conductively connected to Field plate 46 in order to reduce the parasitic capacitance between the interconnect 56 and the interconnects 58 and the parasitic capacitance between the interconnect 56 and the gates 26 . Regarding claim 3 , Lian teaches (in view of Lian or Amethystna ) t he semiconductor device of claim 2, wherein: the well resistor is a p-type resistor (in Amethystna ; the second terminal is configured to receive a current from a current source ( second terminal biased thru well contact 36 in second terminal) ; and the field plate is conductively connected to the first terminal (field plate 46 connected conductively to first terminal via drain region 32) . It is also taught in FIG. 22 of Blanchard where p-well 54 is a conductive well. Regarding claim 4 , Lian teaches t he semiconductor device of claim 2, wherein: the well resistor is an n-type resistor (in Lian 20 is an n-type well. Through appropriately setting the first predetermined distance d1, the second predetermined distance d2 and the third predetermined distance d3, the lateral DMOS 100 may have improved breakdown voltage/voltage sustain performance while permitting the well region 20 to be doped with a higher well dopant concentration to further reduce the on resistance Ron. Paragraph [0031], [0036]) ; the first terminal is a higher voltage terminal; the second terminal is a lower voltage terminal; and the field plate is coupled to the first terminal (right side terminal is first terminal which is considered at higher voltage and current flows from drain side to source (second terminal), second terminal being at lower voltage). Regarding claim 5 , Lian teaches , (in view of Blanchard or Amethystna ) in t he semiconductor device of claim 1, wherein the field plate comprises a polysilicon layer ( In Blanchard 70 filed plate is polysilicon . Also, in Amethystna , field plate 46 is polysilicon ). Regarding claim 6 , Lian teaches (in view of Amethystna ) t he semiconductor device of claim 1, wherein the field plate comprises a metal interconnect layer ( 46 comprises a metal interconnect 48 ) . Regarding claim 7 , Lian teaches t he semiconductor device of claim 1, further comprising an isolation trench (70A, 70B and 70C comprised STI) in the semiconductor substrate around the well resistor (around substrate and well as in FIG. 4 ) . Regarding claim 8 , Lian teaches t he semiconductor device of claim 1, wherein the field plate (60B is connected to bias voltage via 60CT) is connected to a voltage source configured to bias the field plate independent of a voltage on terminals of the well resistor (well resistor bias is done thru either 50CT or 40CT) . Regarding claim 9 , Lian teaches a n integrated circuit comprising: a resistor well (20) extending into a semiconductor substrate; a dielectric layer (60A) extending into the resistor well (extending to 70B) ; and a conductive field plate (70C) located over the dielectric layer (70B) ; Lian does not explicitly teach the conductive field plate configured to modulate a majority carrier distribution within the resistor well while the resistor well conducts a current. However, Lian teaches the conductive field plate configured to modulate a majority carrier distribution within the resistor well while the resistor well conducts a current. (the interpretation is that a well which flows current within can be a well resistor. Since current has to be flown from one terminal of the well to another terminal of the well in order for the device to function, the well 20 is considered well resistor. Because of bias differences majority carrier distribution will affect the current flow). This is also taught in FIG. 22 of Blanchard where p-well 54 is a conductive well. With reference to FIG. 4 in Amethystna , well 22 in considered well resistor as current flows from one terminal to the other. Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Lian ’ s semiconductor device with other teaching from Lian or Blanchard or Amethystna so that device characteristics like breakdown voltage can be improved . Regarding claim 10 , Lian teaches (in view of Blanchard or Amethystna ) t he integrated circuit of claim 9, wherein: the resistor well is p-type; the conductive field plate is conductively connected to a low-side terminal of the resistor well; and the conductive field plate is configured to reduce a voltage coefficient of the resistor well ( the thicker oxide of the field plate (70 is the field plate which increases voltage coefficient) at the bottom of the trench is better able to withstand a higher voltage than the thinner oxide near the top of the trench. Therefore, the breakdown voltage is increased , in Paragraph [0017] in Blanchard in order to increase breakdown voltage) . In Amethystna , the second terminal is configured to receive a current from a current source (second terminal biased thru well contact 36 in second terminal) ; and the field plate is conductively connected to the first terminal (field plate 46 connected conductively to first terminal via drain region 32) Regarding claim 11 , Lian teaches t he integrated circuit of claim 9, wherein: the resistor well is n-type (in Lian 20 is an n-type well. Through appropriately setting the first predetermined distance d1, the second predetermined distance d2 and the third predetermined distance d3, the lateral DMOS 100 may have improved breakdown voltage/voltage sustain performance while permitting the well region 20 to be doped with a higher well dopant concentration to further reduce the on resistance Ron. Paragraph [0031], [0036]) ; the conductive field plate is coupled to a high-side terminal of the resistor well ; and the conductive field plate is configured to reduce a voltage coefficient of the resistor well. Also, in Lian , the conductive field plate 70C is configured to increase a voltage coefficient of the resistor well in order for the breakdown voltage/voltage sustain performance, on resistance (Ron) and size etc. to the lateral DMOS 100 to optimize electrical characteristics of the lateral DMOS 100 . Regarding claim 12 , Lian teaches the integrated circuit of claim 9, wherein the conductive field plate includes a polysilicon layer (In Blanchard 70 filed plate is polysilicon. Also, in Amethystna , field plate 46 is polysilicon). . Regarding claim 13 , Lian teaches t he integrated circuit of claim 9, further comprising an isolation trench that conductively isolates the resistor well from the substrate (70A, 70B and 70C comprised STI, in the semiconductor substrate around the well resistor (around substrate and well) as in FIG. 4) . Regarding claim 14 , Lian teaches the integrated circuit of claim 9, wherein the conductive field plate is configured to increase a voltage coefficient of the resistor well ( the thicker oxide of the field plate (70 is the field plate which increases voltage coefficient) at the bottom of the trench is better able to withstand a higher voltage than the thinner oxide near the top of the trench. Therefore, the breakdown voltage is increased , in Paragraph [0017] in Blanchard in order to increase breakdown voltage) . Also, in Lian , the conductive field plate 70C is configured to increase a voltage coefficient of the resistor well in order for the breakdown voltage/voltage sustain performance, on resistance (Ron) and size etc. to the lateral DMOS 100 to optimize electrical characteristics of the lateral DMOS 100 . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT SHEIKH MARUF whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1903 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT M-F, 8am-6pm EDT . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHEIKH MARUF/ Primary Examiner, Art Unit 28 97