Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-9 & 18-23) in the reply filed on 12/08/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8, 10, 18 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nandakumar et al. (Patent. No.: US 5,917,219 A).
Regarding Claim 1, Nandakumar et al. discloses a semiconductor device comprising: a first source/drain region (56) in a doped region, the doped region (62) being in a semiconductor substrate, the semiconductor substrate having an upper surface, the doped region being doped with a first conductivity type (p-type), the first source/drain region (56) being doped with a second conductivity type (n-type) opposite from the first conductivity type (p-type) (Col. 4, L 41-56; Figs. 3A-3D); a first energy barrier modulation region (64) in the doped region (62) and at the upper surface of the semiconductor substrate, the first energy barrier modulation region (64) being doped with the first conductivity type (p-type) (Col. 4, L 41-56; Figs. 3A-3D);
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a channel covering surface region (66) in the doped region (62) and at the upper surface of the semiconductor substrate, the channel covering surface region (66) being doped with the second conductivity type (n-type) (Col. 4, L 41-56; Figs. 3A-3D); and a gate structure (52) over the upper surface, the first energy barrier modulation region (64) and the channel covering surface region (66) underlying the gate structure (52), the first energy barrier modulation region (64) being laterally between the first source/drain region (56) and the channel covering surface region (66) (Col. 4, L 41-56; Figs. 3A-3D).
Regarding Claim 5, Nandakumar et al., as applied to claim 1, discloses the semiconductor device further comprising a second source/drain region (58) in the doped region (62), the second source/drain region (58) being doped with the second conductivity type (n-type), the channel covering surface region (66) being laterally between the first source/drain region (56) and the second source/drain region (58) (Col. 4, L 41-56; Figs. 3A-3D).
Regarding Claim 8, Nandakumar et al., as applied to claim 1, discloses the semiconductor device further comprising: a second source/drain region (58) in the doped region (62), the second source/drain region (58) being doped with the second conductivity type (n-type), the channel covering surface region (66) being laterally between the first source/drain region (56) and the second source/drain region (58); and a second energy barrier modulation region(64) in the doped region (62) and at the upper surface of the semiconductor substrate, the second energy barrier modulation region (64) being doped with the first conductivity type (p-type), the second energy barrier modulation region (64) underlying the gate structure (52), the second energy barrier modulation region (64) being laterally between the second source/drain region (58) and the channel covering surface region (66) (Col. 4, L 41-56; Figs. 3A-3D).
Regarding Claim 10, Nandakumar et al. discloses a method of forming a semiconductor device, the method comprising: forming a channel covering surface region (66) in a doped region (62) in a semiconductor substrate and at an upper surface of the semiconductor substrate, the doped region being doped with a first conductivity type (p-type), the channel covering surface region (66) being doped with a second conductivity type (n-type) opposite from the first conductivity type (Col. 4, L 41-56; Figs. 3A-3D);
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forming a gate structure (52) over the upper surface and over the channel covering surface region (66) (Col. 4, L 41-56; Figs. 3A-3D); forming a first energy barrier modulation region (64) in the doped region (62) and at the upper surface of the semiconductor substrate, forming the first energy barrier modulation region (64) including implanting a first dopant of the first conductivity type (p-type) in the semiconductor substrate underlying the gate structure (52) (Col. 4, L 41-56; Figs. 3A-3D); and forming a first source/drain region (56) in the doped region (62), the first source/drain region (56) being doped with the second conductivity type (n-type), the first energy barrier modulation region (64) being laterally between the first source/drain region (56) and the channel covering surface region (66) (Col. 4, L 41-56; Figs. 3A-3D).
Regarding Claim 18, Nandakumar et al. discloses a semiconductor device comprising: a first p-type source/drain region (56) in an n-type well (62 ) in a semiconductor substrate, the semiconductor substrate having an upper surface (Col. 4, L 6-56; Figs. 3A-3D – although Figs. 3A-3D specifically show an NMOS, a PMOS is also formed side by side wherein the polarities are simply reversed compared to the polarities of the NMOS device);
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a first n-type region (64) in the n-type well (62) and at the upper surface of the semiconductor substrate; a p-type region (66) in the n-type well (62) and at the upper surface of the semiconductor substrate (Col. 4, L 6-56; Figs. 3A-3D); and a gate structure (52) over the upper surface, the first n-type region (64) and the p-type region (66) underlying the gate structure (52), the first n-type region (64) being laterally between the first p-type source/drain region (56) and the p-type region (66) (Col. 4, L 6-56; Figs. 3A-3D).
Regarding Claim 21, Nandakumar et al., as applied to claim 18, discloses the semiconductor device further comprising: a second p-type source/drain region (58) in the n-type well (62), the p-type region (66) being laterally between the first p-type source/drain region (56) and the second p-type source/drain region (58); and a second n-type region (64) in the n-type well (62) and at the upper surface of the semiconductor substrate, the second n-type region (64) underlying the gate structure (52), the second n-type region (64) being laterally between the second p-type source/drain region (58) and the p-type region (66) (Col. 4, L 41-56; Figs. 3A-3D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4, 7 & 23 are rejected under 35 U.S.C. 103 as obvious over Nandakumar et al. (Patent. No.: US 5,917,219 A), as applied to claim 1, claim 5 and claim 18, further in view of Kapre et al. (Patent. No.: US 6,747,318 B1).
Regarding Claim 2, Nandakumar et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the gate structure includes polysilicon of the first conductivity type. However, Kapre et al. teaches the semiconductor device, wherein the gate structure includes polysilicon of the first conductivity type (Col. 6, L 4-55; Figs. 11B & 12B – semiconductor device 70 is a buried channel NMOS transistor; gate structure 78 includes p-doped polysilicon; this helps reduce the amount of current leakage between the gate electrode and the substrate). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Kapre et al. to adapt the semiconductor device, wherein the gate structure of Nandakumar et al. includes polysilicon of the first conductivity type in order to suppress current leakage between the gate electrode and the substrate.
Regarding Claim 3, Modified Nandakumar et al., as applied to claim 1, discloses the semiconductor device further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the first source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the first source/drain region and the first energy barrier modulation region (Kapre et al. - Col. 4, L 58- Col. 5, L 35 and Col. 6, L 4-55; Figs. 5-11B – use of lightly doped drain (LDD) region in order to improve device performance, such as an increase in breakdown voltage, is well known in the art).
Regarding Claim 4, Modified Nandakumar et al., as applied to claim 3, discloses the semiconductor device further comprising a gate spacer along a sidewall surface of the gate structure and over the upper surface of the semiconductor substrate, the LDD region underlying the gate spacer (Kapre et al. - Figs. 9A-11B).
Regarding Claim 7, Nandakumar et al., as applied to claim 5, does not explicitly disclose the semiconductor device, further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the channel covering surface region However, Kapre et al. teaches the semiconductor device further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the channel covering surface region (Col. 4, L 58- Col. 5, L 35 and Col. 6, L 4-55; Figs. 5-11B – use of lightly doped drain (LDD) region in order to improve device performance, such as an increase in breakdown voltage, is well known in the art). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Kapre et al. to adapt the semiconductor device, further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the channel covering surface region of Nandakumar et al. in order to improve device performance, such as an increase in breakdown voltage.
Regarding Claim 23, Nandakumar et al., as applied to claim 18, does not explicitly disclose the semiconductor device, wherein the gate structure includes n-type polysilicon However, Kapre et al. teaches the semiconductor device, wherein the gate structure includes n-type polysilicon (Col. 6, L 4-55; Figs. 10A-12B – semiconductor device is a buried channel PMOS transistor; gate structure includes n-doped polysilicon; this helps reduce the amount of current leakage between the gate electrode and the substrate). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Kapre et al. to adapt the semiconductor device, wherein the gate structure of Nandakumar et al. includes n-type polysilicon in order to suppress current leakage between the gate electrode and the substrate.
Claim 6 is rejected under 35 U.S.C. 103 as obvious over Nandakumar et al. (Patent. No.: US 5,917,219 A), as applied to claim 1, further in view of Feudel et al. (Pub. No.: US 2006/0043430 A1).
Regarding Claim 6, Nandakumar et al., as applied to claim 5, does not explicitly disclose the semiconductor device, wherein no energy barrier modulation region doped with the first conductivity type is laterally between the second source/drain region and the channel covering surface region. However, Feudel et al. teaches the semiconductor device, wherein no energy barrier modulation region doped with the first conductivity type is laterally between the second source/drain region and the channel covering surface region (Par. 0041-0042; Fig. 2d – this prior art teaches an asymmetric design wherein an energy modulation region 211 is present on the source and absent on the drain side; this prior art teaches that such arrangement reduces parasitic capacitance, thereby improving the switching characteristics and also reduced static leakage currents). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Feudel et al. to adapt the semiconductor device, wherein no energy barrier modulation region doped with the first conductivity type is laterally between the second source/drain region and the channel covering surface region of Nandakumar et al. in order to reduce parasitic capacitance, thereby improving the switching characteristics and also reduced static leakage currents.
Claims 9, 19-20 & 22 are rejected under 35 U.S.C. 103 as obvious over Nandakumar et al. (Patent. No.: US 5,917,219 A), as applied to claim 8, claim 18 & claim 21, further in view of Yu (Patent. No.: US 6,432,763 B1).
Regarding Claim 9, Nandakumar et al., as applied to claim 8, does not explicitly disclose the semiconductor device, further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the second energy barrier modulation region.
However, Yu teaches the semiconductor device, further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the second energy barrier modulation region (Col. 7, L 29- Col. 8, L 56; Fig. 14 – lightly doped drain (LDD) region 238, second source/drain region 246, second energy barrier modulation region 234). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu to adapt the semiconductor device, further comprising a lightly doped drain (LDD) region in the doped region and extending laterally from the second source/drain region, the LDD region being doped with the second conductivity type, the LDD region being laterally between the second source/drain region and the second energy barrier modulation region of Nandakumar et al. in order to improve device performance, such as an increase in breakdown voltage.
Regarding Claim 19, Nandakumar et al., as applied to claim 18, does not explicitly disclose the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the first p-type source/drain region, the p-type LDD region being laterally between the first p-type source/drain region and the first n-type region
However, Yu teaches the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the first p-type source/drain region, the p-type LDD region being laterally between the first p-type source/drain region and the first n-type region (Col. 7, L 29- Col. 8, L 56; Figs. 4-14 – p-type lightly doped drain (LDD) region 238, first p-type source/drain region 246, first n-type region 234). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu to adapt the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the first p-type source/drain region, the p-type LDD region being laterally between the first p-type source/drain region and the first n-type region of Nandakumar et al. in order to improve device performance, such as an increase in breakdown voltage.
Regarding Claim 20, Modified Nandakumar et al., as applied to claim 19, discloses the semiconductor device further comprising a gate spacer along a sidewall surface of the gate structure and over the upper surface of the semiconductor substrate, the p-type LDD region underlying the gate spacer (Yu - Col. 7, L 29- Col. 8, L 56; Figs. 4-14 – spacer 232).
Regarding Claim 22, Nandakumar et al., as applied to claim 21, does not explicitly disclose the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the second p-type source/drain region, the p-type LDD being laterally between the second p-type source/drain region and the second n-type region.
However, Yu teaches the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the second p-type source/drain region, the p-type LDD being laterally between the second p-type source/drain region and the second n-type region (Col. 7, L 29- Col. 8, L 56; Figs. 4-14 – p-type lightly doped drain (LDD) region 240, second p-type source/drain region 248, first n-type region 236). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu to adapt the semiconductor device further comprising a p-type lightly doped drain (LDD) region in the n-type well and extending laterally from the second p-type source/drain region, the p-type LDD being laterally between the second p-type source/drain region and the second n-type region of Nandakumar et al. in order to improve device performance, such as an increase in breakdown voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bakhishev (Pub. No.: US 2017/0025457 A1) – This prior art teaches a semiconductor device comprising: a first source/drain region (104/106) in a doped region (114), the doped region being in a semiconductor substrate (116), the semiconductor substrate having an upper surface, the doped region being doped with a first conductivity type (p-type), the first source/drain region (104/106 being doped with a second conductivity type (n-type) opposite from the first conductivity type; a first energy barrier modulation region (111) in the doped region, the first energy barrier modulation region being doped with the first conductivity type (p-type) ; a channel covering surface region in the doped region and at the upper surface of the semiconductor substrate (110); and a gate structure (102) over the upper surface, the first energy barrier modulation region (111) and the channel covering surface region (110) underlying the gate structure (Fig. 1).
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01/21/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893