Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Election of Restriction Requirement filed on 9/5/2025 and IDS filed on 5/31/2023 and 7/18/2024.
Claims 1-18, 21 and 22 are pending.
Election/Restrictions
3. Applicant’s election without traverse of Group I (Claims 1-18, 21, and 22) in the reply filed on 11/04/2025 is acknowledged.
Claim Objections
4. Claims 1 and 21 are objected to because of the following:
In claim 1, line 5, “X-Y” needs to be defined.
In claim 21, line 16, recited limitation “IC layou” should be “IC layout”.
5. Appropriate correction is required.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (U.S. Pub. No. 2021/0100103 A1).
As per claim 1, Chung discloses:
A method, comprising:
receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features (See Para [018], i.e. a first redistribution structure 14 (or a first interconnect structure 14) disposed over the first surface 12-1 of the first substrate 12. The first redistribution structure 14 includes various conductive components, such as metal lines, contacts, and vias, to provide horizontal and vertical electrical routing, See Figure 1, See Figure 2, i.e. 202 - receive a design);
modifying the IC layout such that the modified RDL structure meets a criterion associated with a X-Y ratio gap (See Para [0023]-[0024], i.e. first isolated region…second isolated region…may not have sufficient density to prevent etch loading…inserting dummy…in isolated regions, See Para [0032]-[0044], See Figure 2, i.e. 214- insert the plurality of dummy MIM structure into the design, See Figure 11 –[prior art modify a design layout by inserting dummy fill into isolated region , filling in the region in order to have sufficient density , because the open region is available for dummy fill in x and y opening, it considered X-Y ratio gap as cited above, wherein prior art modify a layout by inserting dummy feature is considered as the modifying as cited above]);
generating a tape-out according to the modified IC layout (See Para [0028]-[0030], i.e. fabricated based on the modified IC design layout); and
fabricating the semiconductor structure according to the modified IC layout defined in the tape-out (See Para [0028]-[0030], i.e. fabricated based on the modified IC design layout, See Figure 2, i.e. 216 – fabricated a semiconductor device based on the modified design).
As per claim 12, Chung discloses all of the features of claim 1 as discloses above wherein Chung also discloses wherein the fabricating the semiconductor structure according to the modified IC layout defined in the tape-out further includes making photomasks according to the modified IC layout defined in the tape-out; and making the semiconductor structure using the photomasks, wherein at least one of the photomasks defines the modified RDL structure that includes the RDL metallic features and dummy features (Para [0028]-[0030], i.e. fabricated based on the modified IC design layout, See Figure 2, i.e. 216 – fabricated a semiconductor device based on the modified design, See [0032]-[0044], See Figure 2, i.e. 214- insert the plurality of dummy MIM structure into the design, See Figure 11).
Allowable Subject Matter
8. Claims 13-18, 21, and 22 are allowed.
9. Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 2-11, the prior art does not teach the limitations of
dependent claim 2, wherein claims 3-11 depend directly and/or indirectly from dependent claim 2.
With respect to claims 13-18: The closest prior art of record Chung et al. (U.S. Pub. No. 2021/0100103 A1) discloses: A method, comprising: receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features formed in a passivation layer over a semiconductor substrate (See Para [018], i.e. a first redistribution structure 14 (or a first interconnect structure 14) disposed over the first surface 12-1 of the first substrate 12. The first redistribution structure 14 includes various conductive components, such as metal lines, contacts, and vias, to provide horizontal and vertical electrical routing, See Figure 1, See Figure 2, i.e. 202 - receive a design), wherein the RDL metallic features include first conductive features longitudinally oriented along a first direction X (See Figure 1, i.e. 130) and second conductive features longitudinally oriented along a second direction Y being orthogonal to the first direction X (See Figure 1, i.e. 150).
The prior art does not disclose the limitations: determining criteria according to manufacturing data, wherein the criteria include a first criterion associated with a X-Y ratio gap and a second criterion associated with an average spacing of the RDL metallic features, wherein the X-Y ratio gap is defined as a difference between a first duty ratio of the first conductive features and a second duty ratio of the second conductive features; modifying the IC layout such that the modified RDL structure satisfies the first and second criteria; and generating a tape-out according to the modified IC layout, as recited in independent claim 13, wherein claims 14-18 depend directly and/or indirectly from independent claim 13.
With respect to claims 21 and 22: The closest prior art of record Chung et al. (U.S. Pub. No. 2021/0100103 A1) discloses: A method, comprising: receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features formed in a passivation layer over a semiconductor substrate (See Para [018], i.e. a first redistribution structure 14 (or a first interconnect structure 14) disposed over the first surface 12-1 of the first substrate 12. The first redistribution structure 14 includes various conductive components, such as metal lines, contacts, and vias, to provide horizontal and vertical electrical routing, See Figure 1, See Figure 2, i.e. 202 - receive a design), wherein the RDL metallic features include first conductive features longitudinally oriented along a first direction X (See Figure 1, i.e. 130) and second conductive features longitudinally oriented along a second direction Y being orthogonal to the first direction X (See Figure 1, i.e. 150).
The prior art does not disclose the limitations: determining criteria according to manufacturing data, wherein the criteria include a first criterion associated with a X-Y ratio gap and a second criterion associated with an average spacing of the RDL metallic features, wherein the X-Y ratio gap is defined as a difference between a first duty ratio of the first conductive features and a second duty ratio of the second conductive features ;modifying the IC layout such that the modified RDL structure satisfies the first and second criteria, wherein the modifying of the IC layout further includes adjusting RDL metallic features of the RDL structure and adding dummy features to the RDL structure; making photomasks according to the modified IC layout; and fabricating the semiconductor structure using the photomasks, as recited in independent claim 21, wherein claim 22 depend on independent claim 21.
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851