DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-11 and 14-19 is/are rejected under 35 U.S.C. 103 as being obvious over Lee (US 2023/0324881. The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Lee is directed to machine learning based process proximity correction method and semiconductor manufacturing method including the same. Lee discloses a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment. (Para, 0020; Fig.1).
Lee discloses in operation S110, a first layout including patterns for manufacturing the semiconductor device may be received. (Para, 0021). Lee explains the first layout may be a layout of an after cleaning inspection (ACI) or in other words, the first layout may be a target layout desired to be obtained in the ACI, which may refer to an inspection after an etching process for substantially forming a pattern on a substrate. (Para, 0021; Fig.1). Lee explains the operation S110 of receiving the first layout may correspond to a process of connecting data of a measurement ACI to the first layout. (Para, 0022; Fig.1). Lee discloses the data of the measurement ACI may be converted into data such as a polygon, a coordinate, and a vertex of the first layout, and the sum of left/right or up/down bias for each edge and the size polygon (i.e. a retarget critical dimension (CD)) may be linked with the data of the instrumentation ACI. (Para, 0022; Fig.1). These disclosures teach and/or suggest the limitation of claim 11, ‘A process proximity effect correction (PPC) method of a PPC correction device for performing PPC of a plurality of patterns using a processor, the method comprising: performing an etching process using a layout of the plurality of patterns; measuring data on an after cleaning inspection critical dimension (ACI-CD) of the etching process before correcting a layout critical dimension (CD)…’
Lee discloses in operation S120, a second layout may be generated by performing a machine learning (ML)-based process proximity correction (PPC) method on the first layout. (Para, 0022). Lee explains a PPC may be used as a method of predicting an ACI CD in an etching process after a photo process and correcting a layout. (Para, 0023). These disclosures teach and/or suggest the limitation of claim 11, ‘ A process proximity effect correction (PPC) method of a PPC correction device for performing PPC of a plurality of patterns using a processor, the method comprising: …training a sensitivity model using the data…’ Lee explains the PPC may refer to a process of compensating for deformation of the shape of a semiconductor pattern due to the influence of characteristics of patterns and the influence of etching skew when etching is performed such as a process of previously compensating for deformation of a shape during etching by previously deforming a shape of a part expected to be deformed through etching with respect to a specific pattern and reflecting the deformation to a layout. (Para, 0023).
Lee explains, in the method of manufacturing the semiconductor device of the present embodiment, the PPC may proceed by performing ML-based inference on features of patterns of the first layout so the second layout generated through the ML-based PPC may be a layout of an after development inspection (ADI). (Para, 0024; Fig.1). Lee discloses the second layout may be a target layout of a photo-resist (PR) desired to be obtained in the ADI, which may refer to an inspection after a photo process for substantially forming a PR pattern on a substrate, and the photo process may include an exposure process and a developing process. (Para, 0024). Lee discloses subsequently, in operation S130, a third layout may be generated by performing an optical proximity correction (OPC) on the second layout and the third layout may be a target layout with respect to patterns on a mask. (Para, 0025; Fig.1). These disclosures teach and/or suggest the limitation of claims 6-9 and 14-15. Lee discloses the final OPC layout may be transferred to a mask team as mask tape-out (MTO) design data to manufacture a mask, and a photo process, an etching process, etc., are performed using the mask to form a pattern on the wafer, and thus the semiconductor device may be manufactured. (Para, 0034). This disclosure and the disclosures and illustrations of Lee as discussed above teach and/or suggest the limitations of claims 17-19.
Lee discloses a flowchart illustrating an operation (e.g., operation S120) of generating a second layout. (Para 0044; Fig.5). Lee discloses operation S120 of generating the second layout may include operations S121-S127. (Para, 0045; Fig.5). Lee discloses in operation S121, features of patterns may be extracted from a first layout and one or more features may be extracted from each of the patterns in an image of the first layout. (Para, 0045; Fig.5). Lee discloses the same type of features or different types of features may be extracted from each of the patterns, where the features may include a characteristic of each of the patterns and an influence received in each of the patterns from adjacent patterns upon etching. (Para, 0045; Fig.5). Lee discloses the characteristic of each of the patterns may be, for example, the size and shape of each of the patterns. (Para, 0045; Fig.5). Lee discloses the features of the patterns may be reduced to several terms, where the characteristic of each of the patterns may be extracted as numerical values such as tone, direction, length, density, sublayer, width and space of neighboring segments in the normal direction, information about next/previous segments, harmonics, etc. (Para, 0046). Lee explains that in operation S121 of extracting the features of the patterns from the first layout may include tagging the features extracted from each of the patterns to each of the patterns. (Para, 0047). Lee explains, an influence applied to each of the patterns during etching may be tagged and given to each of the patterns. (Para, 0047). Lee discloses in operation S122, a prediction model may be generated through ML based on the features of the patterns. (Para, 0048). Lee discloses the prediction model may include a prediction model for each condition such as an area within a wafer where a pattern is located, or, when the pattern is a HARC, a vertical height of the pattern. (Para, 0050). These disclosures and the illustrations of Figure 5 teach and/or suggest the limitation of claim 1, ‘ A process proximity effect correction (PPC) method of a PPC device for performing PPC of a plurality of patterns, the method comprising: training a sensitivity model by inputting a layout image of the plurality of patterns and a layout critical dimension (CD) of the plurality of patterns into a machine learning module…’
Lee discloses after the prediction model is generated, in operation S123, an ACI target having the maximum process margin may be generated by comparing the upper limit value and the lower limit value of the ACI for each condition. (Para, 0051; Fig.5). Lee discloses after generating the ACI target, in operation S124, the first layout corresponding to the ACI target may be corrected, and a layout of the ADI may be generated based on the corrected first layout. (Para, 0052). Lee discloses the layout of the ADI may be generated by adjusting own parts of the patterns, such as sizes, shapes, etc., of the patterns, based on the ACI target and the first layout corresponding thereto. (Para, 0052). Lee discloses a process of generating the layout of the ACI may correspond to a retarget process, and as described above with reference to FIG. 1, may be used as an input of an OPC later. (para, 0052). Lee discloses, thereafter, using the layout of the ADI, in operation S125, the ACI may be predicted through the prediction model or in other words, the layout of the ACI may be output by inputting the layout of the ADI into the prediction model. (Para, 0052). These disclosures and the illustrations of Figures 1 and 5 teach and/or suggest the limitation of claim 1, ‘A process proximity effect correction (PPC) method of a PPC device for performing PPC of a plurality of patterns, the method comprising: …estimating an after cleaning inspection critical dimension (ACI-CD) sensitivity prediction value of the plurality of patterns by inferring an ACI-CD prediction value of the plurality of patterns using the trained sensitivity model…’ and the limitation of claim 10. Moreover, these disclosures teach and/or suggest the limitation of claim 11, ‘A process proximity effect correction (PPC) method of a PPC correction device for performing PPC of a plurality of patterns using a processor, the method comprising: …estimating an ACI-CD sensitivity prediction value using the sensitivity model…’ and the limitation of claim 16.
Lee discloses in operation S126, it may be determined whether the predicted ACI is within an acceptable range by comparing the predicted ACI with the ACI target. (Para, 0053). Lee explains, when a difference between the predicted ACI and the ACI target is less than a preset threshold value, the predicted ACI may be considered to be within the allowable range, and when the difference is greater than the threshold value, the predicted ACI may be considered to be beyond the allowable range. (Para, 0053). Lee discloses when the predicted ACI is within the allowable range (Yes in operation S126), in operation S127, the layout of the ADI may be determined as the second layout, and the process proceeds to operation S130 of generating a third layout. (Para, 0053). Lee discloses when the predicted ACI is beyond the allowable range (No in operation S126), the process proceeds to operation S124 of generating the layout of the ADI. (Para, 0053). Lee discloses before proceeding to the operation S124 of generating the ADI layout, the first layout may be corrected by adjusting the features such as the own features of the patterns, such as sizes, shapes, etc. of the patterns may be adjusted. (Para, 0054). Lee explains, as the features of the patterns are adjusted, features of the influence of the patterns on neighboring patterns may also be updated. (Para, 0054). Lee discloses in operation S124 of generating the layout of the ADI, operation S125 of predicting the ACI through the prediction model, and operation S126 of determining whether the predicted ACI is within the acceptable range may be repeated until the predicted ACI is within the acceptable range, that is, until the predicted ACI approaches the ACI target. (Para, 0055). Lee discloses when the predicted ACI is within the allowable range, a final layout of the ADI, (e.g., the second layout) may be determined. (Para, 0055). Lee discloses thereafter, the process proceeds to operation S130 of generating the third layout, and the OPC may be performed using the second layout. (Para, 0055). These disclosures and the illustrations of Figures 1 and 5 teach and/or suggest the limitation of claim 1, ‘A process proximity effect correction (PPC) method of a PPC device for performing PPC of a plurality of patterns, the method comprising: …and determining a correction rate of the layout CD of the plurality of patterns using the ACI-CD sensitivity prediction value.’ Moreover, these disclosures teach and/or suggest the limitation of claim 11, ‘ A process proximity effect correction (PPC) method of a PPC correction device for performing PPC of a plurality of patterns using a processor, the method comprising: …and determining a correction rate of the layout CD from the estimated sensitivity prediction value.’
Lee illustrates in Figures 6A and 6B diagrams illustrating generation of an after cleaning inspection (ACI) target of FIG. 5 according to an example embodiment. (Para, 0056). Lee discloses in an operation of generating the ACI target of FIG. 5, a condition may include, for example, an area within a wafer where a pattern is located or in other words, an ACI CD of the pattern may appear differently depending on which area in the wafer the pattern is located. (Para, 0057). Therefore, Lee discloses it may be necessary to consider a process margin for each area within the wafer. (Para, 0057). Lee illustrates in Figure 6A, ACI CDs of the patterns located in a center area C, a middle area M, and an edge area E of the wafer may be different from each other. (Para, 0058). Lee discloses in a method of manufacturing the semiconductor device of the present embodiment, the ACI target maximizing the process margin is generated through CD prediction for each area in the wafer, as will be described below. (Para, 0058).
Lee illustrates in Figure 6B, a diagram 600 showing an ACI CD predicted in the corresponding areas, the upper limit value of the ACI CD allowed in a process (hereinafter referred to as the ‘process upper limit value’), and the lower limit value of the ACI CD allowed in the process (hereinafter referred to as the ‘process lower limit value’). (Para, 0059). In addition, Lee illustrates in the diagram 602 the predicted ACI CD of the corresponding areas, with straight lines and heights, and the process upper and lower process limit values. (Para, 0059). Lee explains, a range of the predicted ACI CD of the corresponding areas may correspond to a process variation (PV) band, and by setting an optimal ACI target, a marge of the PV may be maximized. (Para, 0059). Lee discloses the optimal ACI target may be generated as follows. For example, when the predicted ACI of the center area C is the largest, a difference {circle around (1)} between the process upper limit value and the predicted ACI CD of the center area C is calculated. (Para, 0060). Lee also discloses when the predicted ACI of the edge area E is the smallest, a difference {circle around (2)} between the process lower limit value and the predicted ACI CD of the edge area E is calculated. (Para, 0061). Lee discloses, thereafter, the ACI target is generated so that the smaller vale of {circle around (1)} and {circle around (2)} is maximized. (Para, 0061). Lee discloses in the method of manufacturing the semiconductor device according to an embodiment, in order to solve the problem of the insufficient process margin, a CD or an EPE is predicted for each area in the wafer, the difference between the upper limit value and the lower limit value allowed in the process is calculated, and the ACI target maximizing the process marge is generated. (Para, 0061). Lee explains the ACI is predicted through an ML-based PPC using the generated ACI target, and a layout of the ADI (e.g., a second layout) is corrected through a retarget process using the ACI target, thereby securing the consistency of correction of the layout and performing the ML-based PPC that maximizes the process margin. (Para, 0061).
While the recitations of claims 1, 6-11 and 14-19 are not exactly and/or identically disclosed by Lee, one of ordinary skill in the art would have reasonably expected to successfully form a desired and accurate pattern and semiconductor device based on the disclosures of Lee as discussed above, which provides a method of optimizing a pattern being transferred to a semiconductor substrate by incorporating OPC techniques using machine learning for more accurate correction of distortions in the image before the final pattern is formed and transferred to the substrate for fabrication of the semiconductor device.
Allowable Subject Matter
Claims 2-5, 12-13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The disclosures and illustrations of Lee as discussed above fail to teach and/or suggest the limitation of claim 2, ‘The process proximity effect correction method of claim 1, wherein the training the sensitivity model comprises: generating a first output by performing normalization on a convolution operation result on the layout image of the plurality of patterns; performing a scaling operation on the layout CD of the plurality of patterns; and performing a bias operation on the layout CD of the plurality of patterns.’ The disclosures and illustrations of Lee as discussed above also fail to teach and/or suggest the limitation of claim 12, ‘ The process proximity effect correction method of claim 11, wherein the training a sensitivity model comprises: performing normalization on a convolution operation result for a layout image of the plurality of patterns; performing a first operation on the layout CD; and performing a second operation on the layout CD.’ In addition, the disclosures and illustrations of Lee as discussed above fail to teach and/or suggest the limitation of claim 20, ‘ The process proximity effect correction method of claim 17, wherein the ACI-CD sensitivity prediction value is estimated using a spline regression model; and a correction rate of the layout CD is determined from the estimated ACI-CD sensitivity prediction value.’ The prior art fails to provide other relevant disclosures which are also properly combinable with the disclosures of Lee to teach and/or suggest the limitations of claims 2, 12 and 20. Claims 3-5 and 13 depend directly from claims 2 and 12. Therefore, claims 2-5, 12-13 and 20 include allowable subject matter.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899