DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 03/02/2026. Claims 9-20 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 03/02/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12, 14, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2021/0036002 A1; hereafter LEE) in view of BAE (US 2022/0359560 A1; hereafter BAE).
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Regarding claim 9. LEE discloses a semiconductor device (Fig. [2-4]), comprising:
a stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]) comprising gate conductive layers (Fig. [2,4], conductive pattern CP1 to CPn, Para [ 0043]) and interlayer insulating layers (Fig. [2,4], interlayer insulating layers ILD, Para [ 0043]) alternatively stacked in a longitudinal direction (Fig. [2,4], gate stack structure GST, Para [ 0043]) and storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) penetrating the stack structure in the longitudinal direction (Fig. [2,4], gate stack structure GST, Para [ 0043]), the storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) having a bottom section protruding from a first side of the stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]); and
a common source layer (Fig. [2,4], common source line CSL, Para [ 0037]) located on the first side of the stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]);
wherein the storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) comprise a first channel structure (Fig. [2,4], left channel structure CH, Para [ 0045]) having a first bottom section (channel structure CH may include region [P2A], Para [ 0045]), the first bottom section (region [P2A], Para [ 0045]) comprises a first bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]), a first bottom section filling layer (blocking insulating layer BI, Para [ 0046]) and a first dielectric section ( a tunnel insulating layer TI, Para [ 0046]) on an inner side of the first bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]).
But LEE does not disclose explicitly wherein the first bottom section channel layer, the first bottom section filling layer and the first dielectric section extend beyond the first side of the stack structure into the common source layer.
In a similar field of endeavor, BAE discloses wherein the first bottom section channel layer (Fig [3A, 3B], channel 123, Para [ 0045]), the first bottom section filling layer and the first dielectric section (Fig [3A, 3B], memory pattern121 includes blocking insulating layer BI and tunnel insulating layer TI, para [ 0046]) extend beyond the first side of the stack structure (GST stack structure) into the common source layer (Fig [3A, 3B], common source pattern CSL, Para [ 0045]).
Since LEE and BAE are both from the similar field of endeavor, and BAE discloses memory cell array MCA may include a plurality of bit lines BL, a common source pattern CSL, and a memory block. Therefore, the purpose disclosed by BAE would have been recognized in the pertinent art of LEE. Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE in light of BAE teaching “wherein the first bottom section channel layer (Fig [3A, 3B], channel 123, Para [ 0045]), the first bottom section filling layer and the first dielectric section (Fig [3A, 3B], memory pattern121 includes blocking insulating layer BI and tunnel insulating layer TI, para [ 0046]) extend beyond the first side of the stack structure (GST stack structure) into the common source layer (Fig [3A, 3B], common source pattern CSL, Para [ 0045])” for further advantage such as improving the degree of integration of a device, where etch stop pattern is formed on the sidewall of the filling insulating layer to prevent a portion of the channel layer from being exposed to a back surface of the substrate.
Regarding claim 10. LEE and BAE disclose the semiconductor device of claim 9, LEE further discloses wherein the first bottom section (channel structure CH may include region [P2A], Para [ 0045]) further comprises a first bottom section slit (channel structure CH may include region [P1A], Para [ 0045]) sealed by the first bottom section filling layer (blocking insulating layer BI, Para [ 0046]) and the first dielectric section (a tunnel insulating layer TI, Para [ 0046]).
Regarding claim 11. LEE and BAE disclose the semiconductor device of claim 9, LEE further discloses wherein the storage channel structures (Fig. [2], gate stack structure GST, Para [ 0043]) further comprise a second channel structure (right channel structure CH, Para [ 0045]) having a third bottom section (channel structure CH may include region [P2A], Para [ 0045]), and the third bottom section (region [P2A], Para [ 0045]) comprises a third bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]) and a third bottom section filling layer (blocking insulating layer BI, Para [ 0046]) on an inner side of the third bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]); wherein the common source layer (Fig. [2], common source line CSL, Para [ 0037]) is disposed to contact the third bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]).
Regarding claim 12. LEE and BAE disclose the semiconductor device of claim 11, LEE further discloses wherein the third bottom section further (channel structure CH may include region [P2A], Para [ 0045]) comprises a third bottom section slit (channel structure CH may include region [P1A], Para [ 0045]) located in and sealed by the third bottom section filling layer (blocking insulating layer BI, Para [ 0046]).
Regarding claim 14. LEE and BAE disclose the semiconductor device of claim 9, LEE further discloses wherein the first bottom section channel layer at the first bottom section (channel structure CH may include region [P2A], Para [ 0045]) has a height in the longitudinal direction greater than that of the first bottom section filling layer at the first bottom section in the longitudinal direction (blocking insulating layer BI, Para [ 0046]).
Regarding claim 17. LEE and BAE disclose the semiconductor device of claim 9, LEE further discloses wherein the first bottom section channel layers of any two of the first bottom sections have equal heights in the longitudinal direction (left/ right channel region [P2A], Para [ 0045]).
Regarding claim 18. LEE and BAE disclose the semiconductor device of claim 9, LEE further discloses wherein the semiconductor device further comprises:
a gate line slit structure (Fig. [2,4], slit SI, Para [ 0030]) penetrating the stack structure in the longitudinal direction (Fig. [2,4], gate stack structure GST, Para [ 0043]) and having a slit filler bottom section (Fig. [2,4], sidewall insulating layer 23, Para [ 0036]) protruding from the first side of the stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]).
Regarding claim 20. LEE first embodiment discloses a memory system, comprising:
a memory (Fig. [2,4], Para [ 0022-0026]); and
wherein the memory comprises:
a stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]) comprising gate conductive layers (Fig. [2,4], conductive pattern CP1 to CPn, Para [ 0043]) and interlayer insulating layers (Fig. [2,4], interlayer insulating layers ILD, Para [ 0043]) alternatively stacked in a longitudinal direction (Fig. [2,4], gate stack structure GST, Para [ 0043]) and storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) penetrating the stack structure in the longitudinal direction (Fig. [2,4], gate stack structure GST, Para [ 0043]), the storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) having a bottom section protruding from a first side of the stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]); and
a common source layer (Fig. [2,4], common source line CSL, Para [ 0037]) located on the first side of the stack structure (Fig. [2,4], gate stack structure GST, Para [ 0043]);
wherein the storage channel structures (Fig. [2,4], left/right layers [ ML, CH], construed as storage channel structures, Para [ 0043]) comprise a first channel structure (Fig. [2,4], left channel structure CH, Para [ 0045]) having a first bottom section (channel structure CH may include region [P2A], Para [ 0045]), the first bottom section (channel structure CH may include region [P2A], Para [ 0045]) comprises a first bottom section channel layer (channel structure CH may include region [P2A], Para [ 0045]), a first bottom section filling layer (blocking insulating layer BI, Para [ 0046]) and a first dielectric section ( a tunnel insulating layer TI, Para [ 0046]) on an inner side of the first bottom section channel layer (region [P2A], Para [ 0045]).
But, LEE first embodiment does not disclose explicitly a controller coupled to the memory and configured to control the memory to store data and wherein the first bottom section channel layer, the first bottom section filling layer and the first dielectric section extend beyond the first side of the stack structure into the common source layer.
However, LEE second embodiment disclose a controller coupled to the memory and configured to control the memory to store data (Fig. [19], Para [ 0138-0141] discloses “The memory controller 1110 is configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs overall control operations for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected with the memory system 1100”).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE first embodiment in light of LEE second embodiment teaching “a controller coupled to the memory and configured to control the memory to store data (Fig. [19], Para [ 0138-0141] discloses “The memory controller 1110 is configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs overall control operations for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected with the memory system 1100”)” for further advantage such as control operations for data exchange of the memory system.
But LEE does not disclose explicitly wherein the first bottom section channel layer, the first bottom section filling layer and the first dielectric section extend beyond the first side of the stack structure into the common source layer.
In a similar field of endeavor, BAE discloses wherein the first bottom section channel layer (Fig [3A, 3B], channel 123, Para [ 0045]), the first bottom section filling layer and the first dielectric section (memory pattern121 includes blocking insulating layer BI and tunnel insulating layer TI, para [ 0046]) extend beyond the first side of the stack structure (GST stack structure) into the common source layer (Fig [3A, 3B], common source pattern CSL, Para [ 0045]).
Since LEE and BAE are both from the similar field of endeavor, and BAE discloses memory cell array MCA may include a plurality of bit lines BL, a common source pattern CSL, and a memory block. Therefore, the purpose disclosed by BAE would have been recognized in the pertinent art of LEE. Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE in light of BAE teaching “wherein the first bottom section channel layer (Fig [3A, 3B], channel 123, Para [ 0045]), the first bottom section filling layer and the first dielectric section (Fig [3A, 3B], memory pattern121 includes blocking insulating layer BI and tunnel insulating layer TI, para [ 0046]) extend beyond the first side of the stack structure (GST stack structure) into the common source layer (Fig [3A, 3B], common source pattern CSL, Para [ 0045])” for further advantage such as improving the degree of integration of a device, where etch stop pattern is formed on the sidewall of the filling insulating layer to prevent a portion of the channel layer from being exposed to a back surface of the substrate.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2021/0036002 A1; hereafter LEE) in view of BAE (US 2022/0359560 A1; hereafter BAE) as applied claims above and further in view of LEE (US 2021/0057430 A1; hereafter LEE’430).
Regarding claim 19. LEE and BAE disclose the semiconductor device of claim 9, But, LEE and BAE do not disclose explicitly wherein materials of the first bottom section filling layer and the first dielectric section are the same.
In a similar field of endeavor, LEE’430 discloses wherein materials of the first bottom section filling layer and the first dielectric section are the same (Para [ 0083] discloses “The memory layer 139 may include the blocking insulating layer 131, the data storage layer 133, and a tunnel insulating layer 135 and may include the same materials as the blocking insulating layer BI, the data storage layer DL, and the tunnel insulating layer TI,”).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine LEE and BAE in light of LEE’430 teaching “wherein materials of the first bottom section filling layer and the first dielectric section are the same (Para [ 0083] discloses “The memory layer 139 may include the blocking insulating layer 131, the data storage layer 133, and a tunnel insulating layer 135 and may include the same materials as the blocking insulating layer BI, the data storage layer DL, and the tunnel insulating layer TI,”)” for further advantage such as reduce manufacturing process using same materials and improve device performance.
Allowable Subject Matter
Claims 13 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 13. The semiconductor device of claim 11, wherein the third bottom section channel layer at the third bottom section has a height in the longitudinal direction smaller than that of the first bottom section channel layer at the first bottom section in the longitudinal direction.
Regarding claim 15. The semiconductor device of claim 14, wherein a difference between the height of the first bottom section channel layer at the first bottom section in the longitudinal direction and the height of the first bottom section filling layer at the first bottom section in the longitudinal direction is 15nm to 2μm.
Regarding claim 16. The semiconductor device of claim 14, wherein the first bottom section channel layer and the first bottom section filling layer at the first bottom section and the first dielectric section form a first groove in which the common source layer is disposed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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