DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 - 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Curatola et al. (20190280093).
With regard to claim 17, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) over the substrate (116);
a channel layer (106) of a second semiconductor material over the conductive barrier structure (104);
a barrier layer (108) over the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104);
a trench (referred to as “OP” by examiner’s annotation shown in fig. 1 below; wherein the trench OP is filled with the conductive material 132) between a respective first portion (referred to as “102A” by examiner’s annotation shown in fig. 1 below) of the barrier layer (108), the channel layer (106), and the conductive barrier structure (104) and a respective second portion (referred to as “102B” by examiner’s annotation shown in fig. 1 below) of the barrier layer (108), the channel layer (106), and the conductive barrier structure (104);
a first gate (referred to as “126A” by examiner’s annotation shown in fig. 1 below; wherein the left gate portion 126A is functioning as a first gate) over the first portion (102A) of the barrier layer (108) opposing the channel layer (106);
a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 1 below) coupled to the first portion (102A) of the barrier layer (108) opposing the channel layer (106);
a second gate (referred to as “126B” by examiner’s annotation shown in fig. 1 below; wherein the right gate portion 126B is functioning as a second gate) over the second portion (102B) of the barrier layer (108) opposing the channel layer (106); and
a second electrical contact (118) coupled to the second portion (102B) of the barrier layer (108) opposing the channel layer (106), in which the second electrical contact (118) is coupled to the first electrical contact (132A) via the barrier (108).
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With regard to claim 18, Curatola et al. disclose the channel layer (106) is inherently configurable to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configurable to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects).
With regard to claim 19, Curatola et al. disclose the conductive barrier structure (104) includes an Aluminum Gallium Nitride (AlGaN) layer (for example, paragraphs [0024], [0059]).
With regard to claim 20, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 21, Curatola et al. disclose the conductive barrier structure (104) functioning as a first charge confinement layer (based on the same material AlGaN as Applicant’s the barrier structure); and the first electrical contact (132A) partially penetrates through the first charge confinement layer (104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 4, 7, 8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Prechtl et al. (10388736).
With regard to claim 1, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising: a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106).
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Curatola et al. do not clearly disclose the conductive barrier structure including a first confinement layer, a second confinement layer; and a layer between the first confinement layer and the second confinement layer, the layer having a lower band gap energy than each of the first confinement layer and the second confinement layer.
However, Prechtl et al. disclose the conductive barrier structure (a structure, including layers 100, 101 made of AlN, AlGaN as Applicant’s claim 3. Therefore, the structure, including layers 100, 101 functioning as the conductive barrier structure; for example, see column 9, line 65) including a first confinement layer structure (referred to as “100A” by examiner’s annotation shown in fig. 10 below; wherein the layer 100A made of AlN as Applicant’s claim 3. Therefore, the layer 100A functioning as a first confinement layer structure. Although the applicant uses terms different to those of Prechtl et al. to label the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.), a second confinement layer (referred to as “100B” by examiner’s annotation shown in fig. 10 below; wherein the layer 100B made of AlN as Applicant’s claim 3. Therefore, the layer 100B functioning as a second confinement layer structure); and a layer (referred to as “101A” by examiner’s annotation shown in fig. 10 below) between the first confinement layer (100A) and the second confinement layer (100B), the layer (101A) having a lower band gap energy than each of the first confinement layer (100A) and the second confinement layer (100B). (the layer 101A, made of AlN and inherently having a lower band gap energy than each of the first confinement layer 100A and the second confinement layer 100B wherein the first confinement layer 100A and the second confinement layer 100B are formed from the layer 100 made of AlGaN because Aluminum nitride has a greater bandgap than Aluminum Gallium nitride).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have the conductive barrier structure including a first confinement layer, a second confinement layer; and a layer between the first confinement layer and the second confinement layer, the layer having a lower band gap energy than each of the first confinement layer and the second confinement layer as taught by Prechtl et al. in order to enhance the power transistor excellent in the low-distortion, high-efficiency performance for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, Curatola et al. disclose the channel layer (106) is inherently configurable to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configurable to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects).
With regard to claim 3, Curatola et al. disclose the conductive barrier structure (104) includes an Aluminum Gallium Nitride (AlGaN) layer (for example, paragraphs [0024], [0059]).
With regard to claim 4, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 7, Curatola et al. disclose a conductive structure (referred to as “132B” by examiner’s annotation shown in fig. 1 above; wherein the portion 132B is a portion of the electrical contact structure 132) that penetrates through the barrier layer (108) and coupled to the conductive barrier structure (104).
With regard to claim 8, Curatola et al. disclose the electrical contact (132A) is a first electrical contact and is coupled to the conductive structure (132B), a second electrical contact (118); the gate (126) and the second electrical contact (118) are on a region (referred to as “106A” by examiner’s annotation shown in fig. 1 below) in the channel layer (106); and the first electrical contact (132A) is outside the region (106A).
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With regard to claim 12, Curatola et al. disclose a gate structure (126) comprising a first gate (referred to as “126A” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126A functioning a first gate) and a second gate (referred to as “126B” by examiner’s annotation shown in fig. 1 below; wherein the gate portion 126B functioning a second gate) over the barrier layer (108) opposing the channel layer (106); and a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 1 below; wherein the first electrical contact 132A is a portion of the electrical contact 132) coupled to the barrier layer (108); and a second electrical contact (118) coupled to the barrier layer (108).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Prechtl et al. (10388736) and further in view of Kushida et al. (10680091).
With regard to claim 6, Curatola et al. and Prechtl et al. do not clearly disclose the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct.
However, Kushida et al. discloses the conductive barrier structure (21, 22) includes a quantum well (22) configured to confine a first charge having an opposite polarity (p-type) from a second charge (i-type) that the channel layer (24) is configured to conduct. (for example, see fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al. and Prechtl et al.’s device to have the conductive barrier structure includes a quantum well configured to confine a first charge having an opposite polarity from a second charge that the channel layer is configured to conduct as taught by Kushida et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Prechtl et al. (10388736) and further in view of Lidow et al. (10312131).
With regard to claim 9, Curatola et al. disclose the electrical contact (132A) is a first electrical contact and is coupled to the conductive structure (132B), but Curatola et al. and Prechtl et al. do not clearly disclose a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate via a metal interconnect.
However, Lidow et al. disclose a second electrical contact (205) and a third electrical contact (206) on two sides of the gate (207); and the first electrical contact (208) is electrically coupled to the gate (207) via a metal interconnect (209). (for example, see fig. 20).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al. and Prechtl et al.’s device to have a second electrical contact and a third electrical contact on two sides of the gate; and the first electrical contact is electrically coupled to the gate via a metal interconnect as taught by Lidow et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claim(s) 26 - 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Yanagihara et al. (12284825).
With regard to claim 26, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising: a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and a
gate (126) over the barrier layer (108) opposing the channel layer (106);
a gate structure (126) comprising a first gate (126) over the barrier layer (108) opposing the channel layer (106);
a first electrical contact (referred to as “132A” by examiner’s annotation shown in fig. 1 below) and a second electrical contact (118) coupled to the barrier layer (108).
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Curatola et al. do not clearly disclose a first gate electrode coupled to the first gate; a second gate over the barrier layer opposing the channel layer; a second gate electrode coupled to the second gate; and a first electrical contact and the first gate and the second gate are between the first electrical contact and the second electrical contact.
However, Yanagihara et al. disclose a first gate electrode (22) coupled to the first gate (23); a second gate (27) over the barrier layer (5) opposing the channel layer (4); a second gate electrode (26) coupled to the second gate (27); and the first gate (23) and the second gate (27) are between the first electrical contact (21) and the second electrical contact (28). (for example, see fig. 2B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al.’s device to have a first gate electrode coupled to the first gate; a second gate over the barrier layer opposing the channel layer; a second gate electrode coupled to the second gate; the first gate and the second gate are between the first electrical contact and the second electrical contact as taught by Yanagihara et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 27, Curatola et al. disclose the first semiconductor material includes silicon, and the second semiconductor material includes Gallium Nitride (for example, see paragraph [0023]).
With regard to claim 28, Curatola et al. disclose the channel layer (106) is inherently configured to conduct a charge of a first polarity; and the conductive barrier structure (104) is inherently configured to conduct a charge of a second polarity opposite from the first polarity (for example, paragraph [0059] discloses GaN may be combined with AlGaN or InGaN to form an electron gas inversion region as the channel. The semiconductor device 100 may have AlInN/AlN/GaN barrier/spacer/channel layer structures. In general, the normally-off compound semiconductor transistor can be realized using any suitable III-nitride technology such as GaN that permits the formation of opposite polarity inversion regions due to piezoelectric effects).
With regard to claim 29, Curatola et al. disclose a conductive structure (referred to as “132B” by examiner’s annotation shown in fig. 1 below) coupled between the conductive barrier structure (104), the channel layer (106).
8. Claim(s) 33, 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Lidow et al. (10312131).
With regard to claim 33, Curatola et al. disclose a semiconductor device (for example, figure 1) comprising:
a substrate (116) of a first semiconductor material (for example, paragraph [0023]);
a conductive barrier structure (a conductive barrier layer 104 functioning as a conductive barrier structure) on the substrate (116);
a channel layer (106) of a second semiconductor material on the conductive barrier structure (104);
a barrier layer (108) on the channel layer (106), in which the channel layer (106) is between the barrier layer (108) and the conductive barrier structure (104); and
a gate (126) over the barrier layer (108) opposing the channel layer (106);
a conductive structure (referred to as “132B” by examiner’s annotation shown in fig. 1 above; wherein the portion 132B is a portion of the electrical contact structure 132) that penetrates through the channel layer (106) and the barrier layer (108) and coupled to the conductive barrier structure (104).
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Curatola et al. do not clearly disclose a metal interconnect coupled between the gate and the conductive structure.
However, Lidow et al. disclose a metal interconnect (209) coupled between the gate (207) and the conductive structure (the conductive structure forming in the via 222). (for example, see fig. 20).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al. and Prechtl et al.’s device to have a metal interconnect coupled between the gate and the conductive structure as taught by Lidow et al. in order to enhance the strength of electric field between the drain portion and the source portion for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 34, Curatola et al. disclose a first electrical contact (132A as indicated in fig. 1 above) and a second electrical contact (118) coupled to the barrier layer (108), the first and second electrical contacts (132A, 118) being on opposing sides of the gate (126).
9. Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Curatola et al. (20190280093) in view of Lidow et al. (10312131) and further in view of Bahl (10270239).
With regard to claim 35, Curatola et al. do not clearly disclose a driver circuit having a driver output, a first terminal, and a second terminal, the driver output coupled to the gate, the first terminal coupled to the first electrical contact, and the second terminal coupled to the second electrical contact.
However, Lidow et al. disclose a driver circuit (116) having a driver output (118), a first terminal (120a), and a second terminal (114), the driver output (118) coupled to the gate (G1), the first terminal (120a) coupled to the first electrical contact (the source contact S1 of the transistor 101), and the second terminal (114) coupled to the second electrical contact (the source contact D1 of the transistor 101). (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Curatola et al. and Prechtl et al.’s device to have a driver circuit having a driver output, a first terminal, and a second terminal, the driver output coupled to the gate, the first terminal coupled to the first electrical contact, and the second terminal coupled to the second electrical contact as taught by Bahl in order to provide for normal switching operation as well as protection against overvoltage and/or overcurrent conditions for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
10. Claims 10 – 11, 13 - 16, 22 – 25, 30 - 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10 – 11, 13 - 16, 22 – 25, 30 - 32 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a trench between respective first portions of the barrier layer, the channel layer, and the conductive barrier structure and respective second portions of the barrier layer, the channel layer, and the conductive barrier structure, wherein the gate is a first gate over the first portion of the barrier layer, and the semiconductor device further comprises: a first conductive structure coupled between the first portion of the channel layer and the first portion of the conductive barrier structure; and a second conductive structure coupled between the second portion of the channel layer and the second portion of the conductive barrier structure as recited in claim 10, a first driver circuit having a first driver output and a first terminal, the first terminal electrically coupled to the first electrical contact, and the first driver output coupled to the first gate; and a second driver circuit having a second driver output and a second terminal, the second terminal coupled to the second electrical contact, and the second driver output coupled to the second gate as recited in claim 13, a first trench between a respective first portion of the barrier layer and the channel layer and a respective second portion of the barrier layer and the channel layer; a second trench between the respective first portions of the barrier layer and the channel layer and respective third portions of the barrier layer and the channel layer; wherein the gate is a first gate over the first portion of the barrier layer, a second gate on the first portion of the barrier layer; a first electrical contact and a second electrical contact on the first portion of the barrier layer; a third electrical contact; a first conductive structure coupled between the second portion of the channel layer and the second portion of the conductive barrier structure and to the third electrical contact; a second conductive structure coupled between the third portion of the channel layer and the third portion of the conductive barrier structure; and a fourth electrical contact coupled to the second conductive structure as recited in claim 14; a first semiconductor layer on the surface over the first portion of the barrier layer, a first insulation layer coupled to the first semiconductor layer, and a metal interconnect coupled between the first electrical contact and the first insulation layer as recited in claim 22; a first trench between a respective first portion of the barrier layer and the channel layer and a respective second portion of the barrier layer and the channel layer; a second trench between the respective first portion of the barrier layer and the channel layer and a respective third portion of the barrier layer and the channel layer; wherein: the first gate and the second gate are on the first portion of the barrier layer; the first electrical contact and the second electrical contact are on the first portion of the barrier layer; and the semiconductor device further comprises: a first conductive structure coupled between the second portion of the channel layer and the conductive barrier structure underlying the second portion of the channel layer; a third electrical contact coupled to the first conductive structure; a second conductive structure electrically coupled between the third portion of the channel layer and the conductive barrier structure underlying the third portion of the channel layer; and a fourth electrical contact coupled to the second conductive structure as recited in claim 30, a first driver circuit having a first driver output and a first terminal, the first terminal being coupled to the first electrical contact, and the first driver output being coupled to the first gate; and a second driver circuit having a second driver output and a second terminal, the second terminal being coupled to the second electrical contact, and the second driver output being coupled to the second gate as recited in claim 32.
Response to Amendment
11. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. The indicated allowability of claims 17 - 25 is withdrawn in view of the newly rejection to claims 17 – 25 based on the amended portions of claim 17.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812