DETAILED ACTION
Allowable Subject Matter
Claims 1-14, 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance.
Claim 1 recites in part “a first conductive line connected to the first region and disposed adjacent to the second surface, a second conductive line connected to the fourth region and disposed adjacent to the first surface, …, wherein the photodiode is configured such that a difference between a voltage applied to the first conductive line and a voltage applied to the second conductive line is greater than or equal to a breakdown voltage, and wherein the second conductive line receives a potential supplied from an outside via the fourth conductive line.”
To elaborate briefly on the above, the cited limitations recite wiring layers on two opposite surfaces of substrate, where the two wires provide the two connections to the photodiode, resulting in a breakdown voltage (aka, avalanche mode). Furthermore, one of the wirings gets the potential from outside. This combination of factors has not been found in prior art. The closest prior art that has been found is the US-2022/0155153, by Zhu et al. See FIG. 10A. It shows a “second conductive line” (830) connected to the “fourth region” and disposed adjacent to the “first surface”. However, it is not connected to the “potential supplied from an outside via the fourth conductive line”.
Claim 8 recites similar limitations and is indicated as allowable for similar reasons.
Claims 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 16 recites similar limitations to those of claim 1 and is indicated as allowable subject matter for similar reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2022/0155153) by Zhu et al (“Zhu”).
Regarding claim 15, Zhu discloses in 10A and related text, e.g., an apparatus comprising:
a first substrate (FIG. 5, 2000) having a first surface on which light is incident (best seen in FIG. 10A, surface proximate to 760) and the second surface (FIG. 10A, surface proximate to 750) opposite the first surface; and
a second substrate (FIG. 5, 2010) stacked adjacent to the second surface of the first substrate (see FIG. 5), wherein the first substrate includes an element including
a first region (750) of a first conductivity type (N) and a second region (730) of a second conductivity type (P), a third region (760) in contact with the second region (electrical contact),
a first conductive line (801) connected to the first region and used to read out a signal from the first region (best seen in FIG. 1; the output of diode 10 is connected to “counting unit”; similarly seen in FIG. 22, the physical connection to counting unit from central electrode), and a second conductive line (830) provided adjacent to the first surface and used to supply a potential to the first substrate (by definition; any wirings connected to multiple regions (like 830 is) will supply some sort of potential across the wiring), wherein the first substrate includes a third surface (FIG. 5, top surface of 2010) facing the second surface (bottom surface of 2000), a fourth surface opposite the third surface (bottom surface of 2010), and a transistor formed on (“above”) the fourth surface, and wherein the transistor is a part of a pixel circuit that processes a signal output from the element (transistors are inherent in FIG. 5, 2011/2012/2013; the cited regions “process a signal” in one way or another).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over (US-2022/0155153) by Zhu et al (“Zhu”) in view of (US-2022/0262970) by Murakami et al (“Murakami”).
Regarding claim 18, Zhu discloses in FIG. 10A and related text, e.g., substantially the entire claim structure, as recited in above claims, including the first substrate; the second substrate (see claim 15).
Zhu does not disclose “a first wiring structure stacked adjacent to the second surface of the first substrate; and a second wiring structure disposed between the first wiring structure and the second substrate, wherein a first bonding portion included in the first wiring structure is bonded to a second bonding portion included in the second wiring structure at a bonding plane between the first wiring structure and the second wiring structure, and wherein a first insulating member included in the first wiring structure is bonded to a second insulating member included in the second wiring structure at the bonding plane between the first wiring structure and the second wiring structure”.
Murakami discloses in FIG. 4 and related text, e.g., the first substrate (31); the second substrate (below 73);
a first wiring structure (66) stacked adjacent to the second surface of the first substrate; and
a second wiring structure (71) disposed between the first wiring structure and the second substrate, wherein a first bonding portion (bottom of 66) included in the first wiring structure is bonded to a second bonding portion (top of 71) included in the second wiring structure at a bonding plane between the first wiring structure and the second wiring structure (see FIG. 4), and wherein a first insulating member (around 66) included in the first wiring structure is bonded to a second insulating member (around 71) included in the second wiring structure at the bonding plane between the first wiring structure and the second wiring structure (see FIG. 4).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Zhu with “a first wiring structure stacked adjacent to the second surface of the first substrate; and a second wiring structure disposed between the first wiring structure and the second substrate, wherein a first bonding portion included in the first wiring structure is bonded to a second bonding portion included in the second wiring structure at a bonding plane between the first wiring structure and the second wiring structure, and wherein a first insulating member included in the first wiring structure is bonded to a second insulating member included in the second wiring structure at the bonding plane between the first wiring structure and the second wiring structure”, since applying a known technique (technique of Murakami for how exactly one is to interconnect two computer chips) to a known device ready for improvement (device of Zhu which teaches two chips, but lacks the teaching on how to interconnect them) to yield predictable results (results are predictable because the devices are in the same field (photodiodes) and devices both have two interconnected chips) and result in improved system (the system is improved by providing concrete steps of how to interconnect two chips in a way that is known to function (which Zhu lacks)) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
02/21/26
/Mounir S Amer/Primary Examiner, Art Unit 2818