Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is a response to the amendment filed on 05/27/26. The applicant argument regarding Lars Liebmann is not persuasive; therefore, all the rejections based on Lars Liebmann is retained and repeated for the following reasons.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Oath/Declaration
The oath/declaration filed on May 31th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lars Liebmann (U.S Pub. No. 2021/0319164).
As to claims 1 and 16, the prior art teaches an integrated circuit comprising:
a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors (see fig 1-7 paragraph 0036, 0043-0047; especially, Lars Liebmann teaches a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors as fig 1-7 paragraph 0036, 0044-0046);
wherein at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate is arranged without a diffusion break or dummy gate structure between the standard cells (see fig 7-9 paragraph 0058-0067; especially, Lars Liebmann teaches wherein at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate is arranged without a diffusion break or dummy gate structure between the standard cells as fig 7-9 paragraph 0059-0066);
and wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor (see fig 1-3 and 6-9 paragraph 0066-0077; especially, Lars Liebmann teaches wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor as fig 1-3 and 6-9 paragraph 0067-0076).
As to claim 2, 9 and 16 the prior art teaches wherein each metal gate located at a boundary between the standard cells of the adjoining pair is an active gate (see fig 9-11 paragraph 0054-0060).
As to claim 3, 10 and 17 the prior art teaches wherein the active regions of the transistors in the adjoining pair of standard cells each have a length equal to a distance between a source region and a drain region of the corresponding single transistor (see fig 8-10 paragraph 0058-0063).
As to claim 4, 11 and 18 the prior art teaches wherein comprises a source region or a drain region at an edge adjacent to the other standard cell of the adjoining pair. (see fig 8-10 paragraph 0071-0074).
As to claim 5, 12 and 19 the prior art teaches wherein the source region or the drain region at the edge is shared by the standard cells of the adjoining pair (see fig 1-7 paragraph 0044-0050).
As to claim 6, 13 and 20 the prior art teaches 6wherein the plurality of standard cells comprises a given group of instantiated standard cells that form an L-shape that provides available on-die area for another non-instantiated standard cell (see fig 1-3 and 7-9 paragraph 0056-0061)
As to claim 7 and 14 the prior art teaches wherein the non-planar transistors comprise pairs of transistors with channels of opposite doping polarities, and only one transistor of each pair is adjacent to a silicon substrate (see fig 6-11 paragraph 0085-0091).
As to claim 8 the prior art teaches a method comprising:
forming a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non-planar transistors by: forming, in an integrated circuit of at least one of the one or more of the standard cells, a first transistor with a first channel oriented in a first direction (see fig 1-7 paragraph 0036, 0044-0050);
forming, in the integrated circuit, an oxide layer adjacent to the first transistor (see fig 1-3 and 6-9 paragraph 0063-0069);
forming, in the integrated circuit, a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction (see fig 7-9 paragraph 0058-0067 and 0081-0085);
forming active regions of transistors of the plurality of standard cells, wherein active regions of transistors in at least one adjoining pair of standard cells of the plurality of standard cells are each formed across a single gate terminal of a corresponding single transistor; and arranging, in the integrated circuit, the plurality of standard cells such that the at least one adjoining pair of standard cells is arranged without a diffusion break or dummy gate structure between the standard cells (see fig 1-3 and 6-9 paragraph 0066-0076).
As to claim 15 the prior art teaches a processor comprising: a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks; and computing core circuitry configured to execute the instructions of the one or more tasks using the source data; and wherein the computing core circuitry includes an integrated circuit comprising: a plurality of standard cells (see fig 6 element 606), one or more of the standard cells comprising non planar transistors (see fig 1-7 paragraph 0036, 0043-0047);
wherein at least one adjoining pair of standard cells of the plurality of standard cells, is arranged without a diffusion break or dummy gate structure between the standard cells; and (see fig 1-3 and 6-9 paragraph 0066-0076);
wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor (see fig 1-3 and 6-9 paragraph 0066-0076).
Remarks
Applicant’s response and remarks filed on 05/27/26 have been carefully reviewed. Applicant’s arguments have been fully considered but they are not persuasive. Key argument and their response related to the claims are listed as below:
Applicant contends that Lar Liebmann do not describe “a plurality of standard cells with one or more of the standard cells comprising non planar transistors; especially, Lars Liebmann teaches a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors as fig 1-7 paragraph 0036, 0044-0046)” probes as claimed, Examiner respectfully disagrees. The prior art (Lar Liebmann U.S Pub. No. 2021/0319164) do teach a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors (see fig 1-7 paragraph 0036, 0043-0047; especially, Lars Liebmann teaches a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors as fig 1-7 paragraph 0036, 0044-0046).
Applicant contends that Lar Liebmann do not describe “wherein at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate is arranged without a diffusion break or dummy gate structure between the standard cells 6” probes as claimed, Examiner respectfully disagrees. The prior art (Lar Liebmann U.S Pub. No. 2021/0319164) do teach wherein at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate is arranged without a diffusion break or dummy gate structure between the standard cells (see fig 7-9 paragraph 0058-0067; especially, Lars Liebmann teaches wherein at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate is arranged without a diffusion break or dummy gate structure between the standard cells as fig 7-9 paragraph 0059-0066).
Applicant contends that Lar Liebmann do not describe “wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor” probes as claimed, Examiner respectfully disagrees. The prior art (Lar Liebmann U.S Pub. No. 2021/0319164) do teach wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor (see fig 1-3 and 6-9 paragraph 0066-0077; especially, Lars Liebmann teaches wherein active regions of transistors in the adjoining pair of standard cells are each formed across a single gate terminal of a corresponding single transistor as fig 1-3 and 6-9 paragraph 0067-0076).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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