Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This office action is in response to response to application 18/326835 filed on 05/31/23 . Summary of claims Claims 1- 20 are pending. Claims 1- 20 are rejected. Oath /Declaration The oath/declaration filed on May 31 th , 202 3 is acceptable. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lars Liebmann (U.S Pub. No. 2021/0319164 ). As to claims 1 and 16, the prior art teaches a n integrated circuit comprising: a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non planar transistors (see fig 1- 7 paragraph 0036, 004 3-0047) ; wherein each of a plurality of metal gates, within at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate (see fig 1- 3 and 6-9 paragraph 00 59 -00 6 7) . As to claim 2, 9 and 16 the prior art teaches wherein standard cells of the at least one adjoining pair of standard cells have one or more active regions with a length equal to a distance between a source region and a drain region of a single transistor (see fig 9-11 paragraph 0074-0080 ) . As to claim 3 , 10 and 17 the prior art teaches wherein the standard cells of the at least one adjoining pair of standard cells comprise a source region or a drain region at an edge of one of the standard cells (see fig 9-12 paragraph 0086-0092 ) . As to claim 4, 11 and 18 the prior art teaches wherein the standard cells of the at least one adjoining pair of standard cells share the source region or the drain region at the edge (see fig 9-12 paragraph 0091-0094 ) . As to claim 5 , 12 and 19 the prior art teaches wherein the plurality of standard cells comprises a given group of instantiated standard cells that form an L-shape that provides available on-die area for another non-instantiated standard cell (see fig 1-7 paragraph 0036, 0043-0047) . As to claim 6, 13 and 20 the prior art teaches wherein the non-planar transistors comprise pairs of transistors with channels of opposite doping polarities with only one transistor of a corresponding pair of transistors being adjacent to a silicon substrate (see fig 1-7 paragraph 0003-006 and 0042-0046 ) As to claim 7 and 14 the prior art teaches wherein responsive to a potential being applied to an input node of the integrated circuit, one or more of the standard cells convey a current from the input node to an output node of the integrated circuit (see fig 1-7 paragraph 0045-0051 ) . As to claim 8 the prior art teaches a method comprising: forming a plurality of standard cells (see fig 6 element 606) with one or more of the standard cells comprising non-planar transistors by: forming, in an integrated circuit of at least one of the one or more of the standard cells, a first transistor with a first channel oriented in a first direction (see fig 1-7 paragraph 0036, 004 4 -00 50 ) ; forming, in the integrated circuit, an oxide layer adjacent to the first transistor (see fig 1- 3 and 6-9 paragraph 0063-0069 ) ; forming, in the integrated circuit, a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction (see fig 1-3 and 6-9 paragraph 0074-0082 ) ; and arranging, in an integrated circuit, the plurality of standard cells, wherein each of a plurality of metal gates, within at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate (see fig 1-3 and 6-9 paragraph 0059-0067) . As to claim 15 the prior art teaches a processor comprising: a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks; and computing core circuitry configured to execute the instructions of the one or more tasks using the source data; and wherein the computing core circuitry includes an integrated circuit comprising: a plurality of standard cells (see fig 6 element 606) , one or more of the standard cells comprising non planar transistors (see fig 1-7 paragraph 0036, 0043-0047) ; wherein each of a plurality of metal gates, within at least one adjoining pair of standard cells of the plurality of standard cells, is an active gate (see fig 1-3 and 6-9 paragraph 0059-0067) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT flex 7:00Am-8PM . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH C TAT/ Primary Examiner, Art Unit 2851