CTNF 18/326,939 CTNF 76062 DETAILED ACTION This Office Action is in response to the Election filed on February 4, 2026. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Species A, claims 1-12, 17, and 18 in the reply filed on February 4, 2026 is acknowledged. 08-06 Claims 13-16, 19, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, 8-11, 17, and 18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Sumiko (JP-2006134529 A) . In re claim 1, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs below) an apparatus comprising: groups of ferroelectric memory bit cells (13); and memory interface circuitry (7) having processing outputs and memory access Terminals (at 3), the memory access terminals coupled to the groups of ferroelectric memory bit cells, and the memory interface circuitry configured to: provide control signals (8c) via the memory access terminals to perform read operations on the groups of ferroelectric memory bit cells; receive first signals from the groups of ferroelectric memory bit cells via the memory access terminals from the read operations; and for each group of the groups of ferroelectric memory bit cells, provide second signals representing relationships between the first signals received from the group of ferroelectric memory bit cells and a respective reference voltage of the reference voltages at the processing outputs, the reference voltages representing different temperatures (read the translated portions below) Translated paragraphs: MODE-FOR-INVENTION First, a ferroelectric memory device according to Example 1 of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram showing a ferroelectric memory device. As shown in FIG. 1, the ferroelectric memory device 1 includes a memory unit 2, a sense amplifier 3, a column decoder 4, an address buffer 5a, an address buffer 5b, a row decoder 6, an input / output buffer circuit 7, a control circuit 8a, In addition, an evaluation circuit unit 9 is provided. The memory unit 2 is composed of a first memory cell array A11 and a second memory cell array B12, and the memory cell array A11 and memory cell array B12 are composed of FeRAM. The memory cell array A11 includes a plurality of memory cells 13 connected to the word line WL, the plate line PL, and the bit line BL in the vertical and horizontal directions, and various information is written and read out. The memory cell 13 includes, for example, one transistor and one ferroelectric capacitor (1Tr./1Cap.). The transistor and the ferroelectric capacitor are connected in cascade between the bit line BL and the plate line PL, and the gate of the transistor is connected to the word line WL. The configuration of the memory cell 13 is 1Tr. / 1Cap. Instead of 2Tr. / 2Cap. It may be. The memory cell array B12 has a plurality of memory cells 13 connected to the word line WL, the plate line PL, and the bit line BL in the vertical and horizontal directions, and stores evaluation information and error information of the memory cell array A11. When the amount of information stored in the memory cell array A11 is small, the memory cell array B12 may have a Ferro Fuse structure for one word line WL. The sense amplifier 3 is provided between the memory unit 2 and the column decoder 4, amplifies the read data stored in the memory cell array A 11, and outputs the amplified data to the input / output buffer circuit 7 via the column decoder 4. The column decoder 4 is provided in contact with the sense amplifier 3, receives a signal from the address buffer 5a, and transmits the signal to the memory unit 2 (bit line BL). The address buffer 5a receives the signal output from the control circuit 8a and transmits the signal to the column decoder 4. The address buffer 5 b receives the signal output from the control circuit 8 a and transmits the signal to the row decoder 6. The row decoder 6 is provided in contact with the memory unit 2, receives a signal from the address buffer 5b, and transmits the signal to the memory unit 2 (word line WL). The control circuit 8a receives various control signals transmitted from the outside and transmits the signals to the address buffer 5a and the address buffer 5b. The input / output buffer circuit 7 receives an external signal, transmits the signal to the memory unit 2 via the column decoder 4, and outputs the data stored in the memory unit 2 to the outside via the sense amplifier 3. . The evaluation circuit unit 9 includes a control circuit 8b and a temperature sensing circuit 14. The temperature sensing circuit 14 includes a band gap temperature sensing circuit 15, a gain circuit 16, and an ADC (Analog to Digital Converter) 17. The band gap temperature sensing circuit 15 has a circuit configuration with small dependency on the high-potential-side power supply voltage and the operating temperature, and when the first control signal Z is input and the signal level of the control signal Z is “High” level. In operation, the chip temperature of the memory unit 2 is sensed, and the operation is stopped when the signal level of the control signal Z is “Low” level. Here, the band gap temperature sensing circuit 15 is configured by a CMOS, for example, but may be configured by using a bipolar transistor. The gain circuit 16 receives the data (chip temperature information of the memory unit 2) output from the band gap temperature sensing circuit 15 and performs an amplification operation. The ADC 17 receives the signal output from the gain circuit 16 and digitally converts the signal. Here, in order to classify the chip temperature data of the memory unit 2 with high accuracy, the number of bits of the ADC 17 is preferably large, for example, 13 bits. The control circuit 8b receives the signal (chip temperature data of the memory unit 2) output from the ADC 17, and writes the chip temperature data of the memory cell array to the memory cell array B12 via the address buffer 5a and the address buffer 5b. The control circuit 8b receives the second control signal Y, reads FeRAM evaluation information such as chip temperature data of the memory cell array written in the memory cell array B12 based on the second control signal Y, and inputs the sense amplifier 4 and the input / output The information is output to the outside via the buffer circuit 7. Here, the timing at which the chip temperature of the memory unit 2 is sensed and stored in the memory cell array B12 is when the power is turned on, when the memory cell is accessed a predetermined number of times, or when a chip temperature storage command for the memory unit 2 is generated from the outside. is there. The predetermined number of accesses to the memory cell is set using a counter (not shown) built in the ferroelectric memory device 1. As described above, in the ferroelectric memory device of this embodiment, the temperature sensing circuit 14 that senses the chip temperature of the memory unit 2 based on the control signal Z and the memory cell array B12 that stores the chip temperature information of the memory unit 2. And are provided. Then, the chip temperature of the memory unit 2 is sensed and stored as needed, and the chip temperature information of the memory unit 2 is output to the outside based on the control signal Y. For this reason, since temperature information is stored for each chip, it is useful when performing FeRAM evaluation and failure analysis. In this embodiment, the FeRAM memory cell 13 is 1Tr. / 1Cap. In the configuration, a chain FeRAM in which a plurality of transistors and a plurality of ferroelectric capacitors are arranged between the bit line BL and the plate line PL, and a word line WL is connected to each gate of the plurality of transistors is used. Also good. MODE-FOR-INVENTION Next, a ferroelectric memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. 2 is a block diagram showing an evaluation circuit section, FIG. 3 is a diagram showing temperature characteristics of the first and second reference voltages, and FIG. 4 is a circuit diagram showing a second reference voltage generation circuit. In this embodiment, the configuration of the temperature sensing circuit of the first embodiment is changed. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described. As shown in FIG. 2, the evaluation circuit unit 9a includes a control circuit 8c and a temperature sensing circuit 14a. The temperature sensing circuit 14a includes an ADC 17a, an amplifier circuit 18, a first reference voltage generation circuit 19a, and a second reference voltage generation circuit 19b. The first reference voltage generation circuit 19a generates the first voltage V1 and has a circuit configuration with a small temperature dependency. For example, the first reference voltage generation circuit 19a includes a band gap regulator circuit, and as shown in FIG. V1 does not change with temperature and is constant. On the other hand, the second reference voltage generation circuit 19b generates the second voltage V2 , and as shown in FIG. 3, the second voltage V2 is linear and has a positive temperature coefficient. It is smaller than the first voltage V1 and larger than the first voltage V1 in the region above room temperature. As shown in FIG. 4, in the second reference voltage generation circuit 19b, a resistor R1 and a resistor R2 are cascaded between a high potential side power source Vdd and a low potential side power source Vss, and a connection between the resistor R1 and the resistor R2 is established. A second voltage V2 is output from the node. Here, the resistors R1 and R2 are preferably resistors having a small voltage coefficient, and the relationship between the temperature coefficient K .sub.R1 1 of the resistor .sub.R1 and the temperature coefficient K .sub.R2 1 of the resistor R2 is: K .sub.R2 1> K .sub.R1 1... Formula (1) It is preferable to use a resistor that is linear and both K .sub.R1 1 and K .sub.R2 1 have a positive value. Alternatively, the relationship between the temperature coefficient K .sub.R1 2 of the resistor .sub.R1 and the temperature coefficient K .sub.R2 2 of the resistor R2 is K .sub.R2 2 <K .sub.R1 2 Formula (2) It is preferable to use a resistor that is linear and both K .sub.R1 2 and K .sub.R2 2 have negative values. The amplifier circuit 18 is a differential amplifier circuit that receives the first control signal Z and has two transistors that form a differential pair. The amplifier circuit 18 receives the first voltage V1 and the second voltage V2, and performs an amplification operation. To do. The amplifier circuit 18 operates when the signal level of the control signal Z is “High”, and the amplifier circuit 18 stops operating when the signal level of the control signal Z is “Low”. The ADC 17a receives the signal output from the amplifier circuit 18 and digitally converts the signal. The control circuit 8c receives the signal output from the ADC 17a, converts the signal into chip temperature data of the memory cell array, and sends the chip temperature data of the memory unit 2 to the memory cell array B12 via the address buffer 5a and the address buffer 5b. Let it be written. In addition, the control circuit 8c receives the second control signal Y, reads FeRAM evaluation information such as chip temperature data of the memory unit 2 written in the memory cell array B12 based on the second control signal Y, Output to the outside via the output buffer circuit 7. Here, in order to classify the chip temperature data of the memory unit 2 with high accuracy, the number of bits of the ADC 17a is preferably large, for example, 13 bits. As described above, in the ferroelectric memory device of this embodiment, the temperature sensing circuit 14a that senses the chip temperature of the memory unit 2 based on the control signal Z and the memory cell array B12 that stores the chip temperature information of the memory unit 2 are used. And are provided. Then, the chip temperature of the memory unit 2 is sensed and stored as needed, and the chip temperature information of the memory unit 2 is output to the outside based on the control signal Y. For this reason, it has the same effect as Example 1. In the present embodiment, the control circuit 8c converts the chip temperature data of the memory unit 2; however, a converter is provided between the ADC 17a and the control circuit 8c, and the signal output from the ADC 17a is converted to the chip of the memory unit 2. You may convert into temperature data. Further, a converter may be provided between the amplifier circuit 18 and the ADC 17a. In this case, the converter will convert the analog quantity. DESCRIPTION OF SYMBOLS 1, 1a Ferroelectric memory device 2 Memory part 3 Sense amplifier 4 Column decoder 5a, 5b Address buffer 6 Row decoder 7 Input / output buffer circuit 7a Input buffer circuit 7b Output buffer circuit 8a, 8b, 8c, 8d, 8e, 8f Control Circuits 9, 9a, 9b, 9c Evaluation circuit unit 11 Memory cell array A 12 Memory cell array B 13 Memory cell 14, 14a Temperature sensing circuit 15 Band gap temperature sensing circuit 16 Gain circuit 17, 17a, 17b ADC BL Bit line PL Plate line WL Word line In re claim 2, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) the memory interface circuitry is configured togenerate the second signals based on comparing the first signals from different groups of the groups of ferroelectric memory bit cells with the reference voltages (read the translated sections above). In re claim 3, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) each ferroelectric memory bit cell of the groups of ferroelectric memory bit cells has a respective word terminal (WL) and a respective plate terminal (PL), the plate terminals of the groups of ferroelectric memory bit cells coupled to respective terminals of the memory access terminals; the apparatus further comprises groups of switches and bit lines; and each switch of each group of the groups of switches coupled between the plate terminal of a respective ferroelectric memory bit cell of a respective group of ferroelectric memory bit cells and a respective bit line of the bit lines, the switches having control terminals coupled to respective word terminals. In re claim 4, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) wherein the memory interface circuitry includes comparators configured to generate the second signals based on comparing the first signals from different groups of the groups of ferroelectric memory bit cells with the reference voltages, each of the comparators has a first input, a second input, and a comparator output, the first input of each of the comparators coupled to a respective bit line of the bit lines, the comparator outputs coupled to the processing outputs, and each of the comparators is configured to: receive a respective signal of the first signals from a respective group of ferroelectric memory bit cells at its first input; receive a respective reference voltage of the reference voltages at its second input; and provide a respective signal of the second signals at its comparator output (read the translated excerpts above). In re claim 5, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) the memory interface circuitry is configured to perform read operations on each group of the groups of ferroelectric memory bit cells based on: providing, as part of the control signals, selection signals to enable each group of the groups of switches to connect the plate terminals of respective groups of ferroelectric memory bit cell to a respective bit line of the bit lines sequentially at different times; providing, as part of the control signals, pulse signals to the plate terminals of the respective groups of ferroelectric memory bit cell sequentially at different times; and after each of the pulse signals, enabling each comparator to compare the first signal provided by each ferroelectric memory bit cell of the group of ferroelectric memory bit cells with the respective reference voltage of the reference voltages to generate the second signal for ferroelectric memory bit cell (read the translated excerpts above). In re claims 8-11, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) wherein the processing output is a first processing output, and the apparatus further comprises a processing circuit having a second processing output, the processing circuit configured to: detect, based on the second signals, a historical temperature excursion event; and provide an indication of the historical temperature excursion event at the second processing output. The processing circuit is configured to provide a third signal based on the second signal representing a temperature of the apparatus in the historical temperature excursion event at the second processing output. The processing circuit is configured to: for each group of the groups of ferroelectric memory bit cells, determine a failure rate based on whether the respective second signals of the group of ferroelectric memory bit cells indicate that the respective first signals of the group of ferroelectric memory bit cells exceeds or is below the respective reference voltage of the reference voltages; and determine the temperature based on the failure rates and the reference voltages. The processing circuit is configured to determine the temperature based on: determining, based on the failure rates and the reference voltages, an average reference voltage that results in at least a threshold failure rate among the groups of ferroelectric memory bit cells; and determining the temperature based on the average reference voltage (read the translated excerpts). In re claim 17, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) a method comprising: providing, by a sensor (14), control signals (8c) to perform read operations on groups of ferroelectric memory bit cells (13); receiving, by the sensor, first signals from the groups of ferroelectric memory bit cells responsive to the read operations; and for each group of the groups of ferroelectric memory bit cells, providing, by the sensor, second signals representing relationships between the first signals received from the group of ferroelectric memory bit cells and a respective reference voltage of reference voltages, the reference voltages representing different temperatures (read the translated excerpts above). In re claim 18, Sumiko discloses (Figs. 1, 2), MODE-FOR-INVENTION (1st and 2nd); see the translated paragraphs above) receiving, by a processor, the second signals; detecting, by the processor, a historical temperature excursion event based on the second signals; and outputting, by the processor, an indication of the historical temperature excursion event . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 6, 7 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hirano (US 6,449,183 B1), Summerfelt (US Pub. 2024/0407175 A1), Vimercati (US Pub. 11,616,068 B1), Karpov (WO-2018063375 A1) and (JP-2024508453 A) also disclose various elements of the claims . Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817 Application/Control Number: 18/326,939 Page 2 Art Unit: 2817 Application/Control Number: 18/326,939 Page 3 Art Unit: 2817 Application/Control Number: 18/326,939 Page 4 Art Unit: 2817 Application/Control Number: 18/326,939 Page 5 Art Unit: 2817 Application/Control Number: 18/326,939 Page 6 Art Unit: 2817 Application/Control Number: 18/326,939 Page 7 Art Unit: 2817 Application/Control Number: 18/326,939 Page 8 Art Unit: 2817 Application/Control Number: 18/326,939 Page 9 Art Unit: 2817 Application/Control Number: 18/326,939 Page 10 Art Unit: 2817 Application/Control Number: 18/326,939 Page 11 Art Unit: 2817
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