DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1-20 are pending, independent claims 1 and 10 and dependent claims 3 and 11 are amended, claim 2 is cancelled.
Applicant’s arguments on page 10, filed 12/29/2025, with respect to U.S.C. 112(b) rejections of claims 6 and 12 have been fully considered and are persuasive. The U.S.C. 112(b) rejections of claims 6 and 12 have been withdrawn.
Applicant’s arguments on pages 10-12, filed 12/29/2025 with respect to U.S.C. 101 rejection of claims 1-20 have been fully considered but they are not considered persuasive.
Applicant argues that claimed invention provides a technical solution for verifying the correctness of the source data so that the reliability of the test system can be effectively improved and the technicality of claimed invention is significantly more the abstract idea per se.
Although the recited abstract limitations may improve the result output by a computer (i.e., test system), there is no improvement in the functioning of said computer (test system). Similar to the reasoning applied in the Federal Circuit Court decision in the Electric Power Troup LLC v. Alstom S.A. case of August 1, 2016, page 8, “In Enfish, we applied the distinction to reject the § 101 challenge at stage one because the claims at issue focused not on asserted advances in uses to which existing computer capabilities could be put, but on a specific improvement—a particular database technique—in how computers could carry out one of their basic functions of storage and retrieval of data. Enfish, 822 F.3d at 1335–36; see Bascom, 2016 WL 3514158, at *5; cf. Alice, 134 S. Ct. at 2360 (noting basic storage function of generic computer). The present case is different: the focus of the claims is not on such an improvement in computers as tools, but on certain independently abstract ideas that use computers as tools.” No specific computer improvement, such as to how computers could carry out an improved version one of their basic functions of storage and retrieval of data, is present in the claims of the instant application; therefore, the claims in the instant application are an example of an abstract idea that uses computers as tools. For at least these reasons, Applicant' s arguments are not persuasive.
Applicant argues that reference circuit and one or more testing circuits, the test system, the main control unit, the control host and the analyzer should be considered as significantly more than generic computer elements and thus the claimed invention should be significantly more than the abstract idea.
Examiner noted in the rejection below, the limitations that are to an abstract idea. The inclusion of that reference circuit and one or more testing circuits, the test system, the main control unit, the control host and the analyzer does not make an abstract limitation non-abstract. Additionally, that reference circuit and one or more testing circuits, the test system, the main control unit, the control host and the analyzer are all generic computer elements, easily found and utilized and not considered significantly more than the abstract idea. As recited in the MPEP, 2106.05(b), merely adding a generic computer, generic computer components, or a programmed computer to perform generic computer functions does not automatically overcome an eligibility rejection. Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 134 S. Ct. 2347, 2359-60, 110 USPQ2d 1976, 1984 (2014). See also OIP Techs. v. Amazon.com, 788 F.3d 1359, 1364, 115 USPQ2d 1090, 1093-94.
Applicant’s arguments on pages 10-12, filed 12/29/2025 with respect to U.S.C. 103 rejection of claims 1-20 have been fully considered but they are not considered persuasive.
Applicant argues McCoy fails to teach the "two-stage verification" in which the measured uncorrected data is compared with a raw data boundary setting (i.e., a first stage), and then a result of the relative comparison is compared with a verification boundary setting (i.e., a second stage) for verifying the measured uncorrected data.
Examiner respectfully disagrees. McCoy teaches the first stage of verification in [0034] by first calculating the upper and lower compliance variation limits may be calculated from the verification standards database. McCoy discusses the creation of this data base in [0033] “Verification coupons 76 are traces that are thoroughly characterized with known good S-parameter measurements. In some embodiments, verification coupons 76 are measured across many calibration cycles to generate a database of verification standards that are stored in data storage module 20. Verification coupons 76 may be measured with probes 22a and 22b or in a separate test system to generate the database.”. [0034] “Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting).” Then the second stage of testing is to provide these compliance boundaries to future calibrations where McCoy further states [0034] “For example, the calibrations may be deemed to have passed if the measurements fall within the range defined by and including the upper and lower compliance limits. If the measurements fall outside the range defined by the upper lower compliance limits, the calibration may be deemed to have failed.” For at least these reasons, Applicant’s argument is unpersuasive.
Applicant argues that there is no motivation to combine Tang and McCoy since the person having ordinary skill in the art cannot combine the calibration method for the testing system having the probes in Tang with the verification method for printed wiring board disclosed in McCoy.
Examiner respectfully disagrees. Applicant states that Tang teaches a background art of the claimed invention when it measures the responsive signals based on the excitation signals provided by the testing system through the probes and uses the error model to ensure the characteristics of DUT in the future, following said logic, one of ordinary skill in the art would know of the background knowledge taught by Tang and would be more than capable of applying it to the data verification process happening in McCoy. Furthermore, McCoy in [0008] discusses the use of calibration standard to verify the compliance range of the s-parameter measured by the circuit. For at least these reasons, Applicant’s argument is unpersuasive.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101. The claimed invention is directed to the abstract concept of performing mental steps without significantly more. The claim(s) recite(s) the following abstract concepts in BOLD of
Claim 1. A method for data verification which is to validate data generated by a test system during a calibration process, comprising:
inputting, via a probe assembly of the test system, incident data from a main control unit of the test system to a calibration standard assembly having two or more testing circuits;
obtaining, by the main control unit, a measured uncorrected data by measuring the incident data through the two or more testing circuits; and
comparing the measured uncorrected data with a raw data boundary setting,
performing relative comparison on any two sets of the measured uncorrected data outputted from at least two testing circuits of the calibration standard assembly;
and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data;
wherein, one of the testing circuits is selected as a reference circuit and another one of the testing circuits is selected as a second testing circuit, so as to verify the measured uncorrected data outputted from the second testing circuit.
Claim 10. A test system that performs a method for data verification which is to validate data generated by the test system during a calibration process, comprising:
a main control unit including a control host and an analyzer;
a probe assembly including at least one probe-head having one or more probe tips and at least one cable linked to the analyzer;
wherein the probe assembly is configured to contact one of testing circuits of a calibration standard assembly via the one or more probe tips for performing a calibration process with an incident data generated by the control host;
wherein the test system performs the method for data verification by the control host, and the method comprises:
inputting, via the probe assembly of the test system, incident data from the main control unit of the test system to the calibration standard assembly having two or more testing circuits;
obtaining, by the control host, a measured uncorrected data by measuring the incident data through the two or more testing circuits; and
comparing the measured uncorrected data with a raw data boundary setting,
performing relative comparison on any two sets of the measured uncorrected data outputted from at least two testing circuits of the calibration standard assembly;
and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data;
wherein, one of the testing circuits is selected as a reference circuit and another one of the testing circuits is selected as a second testing circuit, so as to verify the measured uncorrected data outputted from the second testing circuit.
Under step 1 of the eligibility analysis, we determine whether the claims are to a statutory category by considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: process, machine, manufacture, or composition of matter. The above claims are considered to be in a statutory category.
Under Step 2A, Prong One, we consider whether the claim recites a judicial exception (abstract idea). In the above claim, the highlighted portion constitutes an abstract idea because, under a broadest reasonable interpretation, it recites limitation the fall into/recite abstract idea exceptions. Specifically, under the 2019 Revised Patent Subject Matter Eligibility Guidance, it falls into the grouping of subject matter that, when recited as such in a claim limitation, covers performing mathematics or mental steps.
Next, under Step 2A, Prong Two, we consider whether the claim that recites a judicial exception is integrated into a practical application. In this step, we evaluate whether the claim recites additional elements that integrate the exception into a practical application of that exception.
This judicial exception is not integrated into a practical application because there is no improvement to another technology or technical field; improvements to the functioning of the computer itself; a particular machine; effecting a transformation or reduction of a particular article to a different state or thing. Examiner notes that since the claimed methods and system are not tied to a particular machine or apparatus, they do not represent an improvement to another technology or technical field. Similarly, there are no other meaningful limitations linking the use to a particular technological environment. Finally, there is nothing in the claims that indicates an improvement to the functioning of the computer itself or transform a particular article to a new state.
Finally, under Step 2B, we consider whether the additional elements are sufficient to amount to significantly more than the abstract idea.
The additional element of inputting incident data from a main control unit of the test system to a calibration standard assembly having two or more testing circuits; and obtaining a measured uncorrected data by measuring the incident data through the two or more testing circuits; and contacting (i.e., touching) one of testing circuits for performing a calibration process are considered necessary data gathering and is not sufficient to integrate the abstract idea into a practical application. As recited in MPEP section 2106.05(g), necessary data gathering (i.e., receiving data) is considered extra solution activity in light of Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015).
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a probe assembly with probe tips are well known and well utilized in the field of the pending application, and thus recite what is considered field of use or technological environment in which when applied to the judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a test system, main control unit, a control host and an analyzer, and cables are generic computer elements and not considered significantly more than the abstract idea. As recited in the MPEP, 2106.05(b), merely adding a generic computer, generic computer components, or a programmed computer to perform generic computer functions does not automatically overcome an eligibility rejection. Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 134 S. Ct. 2347, 2359-60, 110 USPQ2d 1976, 1984 (2014). See also OIP Techs. v. Amazon.com, 788 F.3d 1359, 1364, 115 USPQ2d 1090, 1093-94.
Claim 4 recites wherein any of the two or more testing circuits mounted on a calibration substrate is configured to be contacted by one or more probe tips of at least one probe assembly of the test system. Claims 7 and 18 recite inputting the data to the calibration standard assembly; and repeatedly measuring uncorrected data through the two or more testing circuits of the calibration standard assembly. Claim 13 recites wherein, under a reflection mode, the analyzer processes signals received by at least one port via a signal terminal and a ground terminal of the at least one probe-head of the probe assembly; and, under a transmission mode, the analyzer processes the signals received by two or more ports via signal terminals and ground terminals of the at least one probe-head of the probe assembly. These claims recite what is considered necessary data gathering and outputting and is not sufficient to integrate the abstract idea into a practical application.
Claims 6 and 12 recites wherein the two or more testing circuits are selected from a group essentially consisting of an AIR testing circuit, an OPEN testing circuit, a SHORT testing circuit, a LOAD testing circuit, a THROUGH testing circuit and a LINE testing circuit; and the measured uncorrected data is produced based on a corresponding standard measurement which is selected from an AIR standard, an OPEN standard, a SHORT standard, a LOAD standard, a THROUGH standard and a LINE standard. Claim 15 recites wherein the series of frequency responses are expressed by a frequency response diagram displayed on a display device of the main control unit, and a verification boundary setting used to verify the measured uncorrected data is illustrated by a series of threshold as a boundary line shown in the frequency response diagram. These claims recite what is considered extra solution activity that is not sufficient to integrate the abstract idea into a practical application.
Claim 16 recites a computer-implemented adjustment tool. These claims recite what is considered generic computer elements and not sufficient to integrate the abstract idea into a practical application.
Claims 2, 3, 5, 8, 9, 11, 14, 17, 19, and 20 further limit the abstract ideas without integrating the abstract concept into a practical application or including additional limitations that can be considered significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 3-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2011/0208467 A1 cited in IDS on 8/26/2025) in view of McCoy et al. (US 2011/0131030 A1) hereinafter McCoy.
Regarding Claim 1, Tang teaches inputting, via a probe assembly of the test system, incident data from a main control unit of the test system to a calibration standard assembly having two or more testing circuits ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) (i.e., probe assembly data) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) (i.e., incident data/signal from a main control unit) through one of the probes, and responsive signals are measured by the testing system through both probes.” Where [0064] “The method may begin, in block 1002, by providing one or more calibration standards ( e.g., calibration standards 400-404, 700-704, FIGS. 4, 7) (i.e., two or more testing circuits) that include end structures, in accordance with various embodiments previously described.”); obtaining, by the main control unit, a measured uncorrected data by measuring the incident data through the two or more testing circuits ([0065] “In block 1008, the responsive signals are analyzed to determine an electrical characteristic (e.g., an S-parameter) of the test setup. The determined electrical characteristic includes a characteristic of the testing system (e.g., VNA, cables, and probes). The responsive signals may include, for example, measurements of the amplitudes of forward and/or reverse waves traveling to/from the calibration standard's ports.”, Where a VNA(vector network analyzer) measures the performance of electrical components and circuits by sending a test signal into a device and measuring both the reflected and transmitted signals across a range of frequencies); and performing relative comparison on any two sets of the measured uncorrected data outputted from at least two testing circuits of the calibration standard assembly ([0066] “In block 1010, calibration of the testing system is completed by generating an error model of the testing system ( e.g., by a processing system associated with the VNA or a separate computer) using the electrical parameters determined (i.e., electrical parameters like s-parameters measure the ratio of incident to reflected or transmitted power waves at its ports of each circuit) in blocks 1004-1009.” Where [0065] “In block 1009, a determination is made whether all calibration standards have been tested. If not, the process iterates as shown. (i.e., measuring multiple calibration circuits); wherein, one of the testing circuits is selected as a reference circuit and another one of the testing circuits is selected as a second testing circuit, so as to verify the measured uncorrected data outputted from the second testing circuit ([0067] “In block 1012, electrical parameters of a DUT are then determined using the "calibrated" testing system. According to an embodiment, this may include contacting the probe tips to test pads of the DUT, providing excitation signals, and measuring responsive signals ( e.g., using the VNA). Because the electrical parameters of the DUT are measured with the calibrated testing system, the DUT's live electrical parameters can be accurately determined.” Where in previous steps 1006-1008 the calibration circuits or reference circuits are used).
Tang does not teach comparing the measured uncorrected data with a raw boundary setting, and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data.
McCoy teaches comparing the measured uncorrected data with a raw boundary setting ([0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.”), and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data ([0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 10, Tang teaches, a main control unit including a control host and an analyzer ([0022] “Testing system 200 includes a vector network analyzer 208 (VNA) (i.e., main control unit),” where a vector network analyzer (VNA) system consists of both a control host and an analyzer section. In a VNA, the control host is either an integrated component, consisting of a built-in computer, display, and keypad, or on a separate computer as stated in [0066] “( e.g., by a processing system associated with the VNA or a separate computer)”); a probe assembly including at least one probe-head having one or more probe tips and at least one cable linked to the analyzer (Fig 2 where there are 2 probes, with their own tips, each with their own cable to the analyzer); wherein the probe assembly is configured to contact one of testing circuits of a calibration standard assembly via the one or more probe tips for performing a calibration process with an incident data generated by the control host ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) through one of the probes, and responsive signals are measured by the testing system through both probes.”); wherein the test system performs the method for data verification by the control host, and the method comprises ([0063] “FIG. 10 illustrates a flowchart of a method for determining electrical parameters of a testing system and an integrated circuit device using a set of calibration standards, according to an example embodiment.”, where the VNA (control host and analyzer) is used to perform the method see [0064-0067]): inputting, via the probe assembly of the test system, incident data from the main control unit of the test system to the calibration standard assembly having two or more testing circuits ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) (i.e., probe assembly data) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) (i.e., incident data/signal from a main control unit) through one of the probes, and responsive signals are measured by the testing system through both probes.” Where [0064] “The method may begin, in block 1002, by providing one or more calibration standards ( e.g., calibration standards 400-404, 700-704, FIGS. 4, 7) (i.e., two or more testing circuits) that include end structures, in accordance with various embodiments previously described.”); obtaining, by the control host, a measured uncorrected data by measuring the incident data through the two or more testing circuits ([0065] “In block 1008, the responsive signals are analyzed to determine an electrical characteristic (e.g., an S-parameter) of the test setup. The determined electrical characteristic includes a characteristic of the testing system (e.g., VNA, cables, and probes). The responsive signals may include, for example, measurements of the amplitudes of forward and/or reverse waves traveling to/from the calibration standard's ports.”, Where a VNA(vector network analyzer) measures the performance of electrical components and circuits by sending a test signal into a device and measuring both the reflected and transmitted signals across a range of frequencies); and verifying the measured uncorrected data by performing relative comparison on any two sets of the measured uncorrected data outputted from at least two of the testing circuits of the calibration standard assembly ([0066] “In block 1010, calibration of the testing system is completed by generating an error model of the testing system ( e.g., by a processing system associated with the VNA or a separate computer) using the electrical parameters determined (i.e., electrical parameters like s-parameters measure the ratio of incident to reflected or transmitted power waves at its ports of each circuit) in blocks 1004-1009.” Where [0065] “In block 1009, a determination is made whether all calibration standards have been tested. If not, the process iterates as shown. (i.e., measuring multiple calibration circuits); wherein, one of the testing circuits is selected as a reference circuit and another one of the testing circuits is selected as a second testing circuit, so as to verify the measured uncorrected data outputted from the second testing circuit([0067] “In block 1012, electrical parameters of a DUT are then determined using the "calibrated" testing system. According to an embodiment, this may include contacting the probe tips to test pads of the DUT, providing excitation signals, and measuring responsive signals ( e.g., using the VNA). Because the electrical parameters of the DUT are measured with the calibrated testing system, the DUT's live electrical parameters can be accurately determined.” Where in previous steps 1006-1008 the calibration circuits or reference circuits are used).
Tang does not teach comparing the measured uncorrected data with a raw boundary setting, and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data.
McCoy teaches comparing the measured uncorrected data with a raw boundary setting ([0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.”), and comparing a result of the relative comparison with a verification boundary setting so as to verify the measured uncorrected data ([0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 3, Tang and McCoy teach the limitations of Claim 1.
Tang does not teach wherein the verification boundary setting and the raw data boundary setting are respectively adjustable and illustrated by a series of thresholds over frequencies or a range between an upper-limit line and a lower-limit line over frequencies.
McCoy teaches wherein the verification boundary setting and the raw data boundary setting are respectively adjustable and illustrated by a series of thresholds over frequencies or a range between an upper-limit line and a lower-limit line over frequencies ([0037] “Adjustable parameter M is a multiplier of variance parameter σ that expands the upper and lower compliance limits by an amount based on the statistical variation of the verifications standard measurements in the verification standards database. That is, adjustable parameter M allows the user to adjust the pass/fail performance bounds by M times the baseline S-parameter variation in the verification standards database.” Where [0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 4, Tang and McCoy teach the limitations of claim 1.
Tang further teaches wherein any of the two or more testing circuits mounted on a calibration substrate is configured to be contacted by one or more probe tips of at least one probe assembly of the test system ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) through one of the probes, and responsive signals are measured by the testing system through both probes”).
Regarding Claim 5 and 14, Tang and McCoy teach the limitations of claim 4 and 10, respectively.
Tang does not teach wherein the measured uncorrected data contains a series of frequency responses that relate to electrical characteristics of the probe assembly of the test system and are expressed in phases or magnitudes over.
McCoy teaches wherein the measured uncorrected data contains a series of frequency responses that relate to electrical characteristics of the probe assembly of the test system and are expressed in phases or magnitudes over frequencies ([0024] “ additional instruments may be used to analyze the magnitude response and/or the phase response of net 13. The instruments may be used instead of or in addition to network analyzer 18 to obtain S-parameter measurements.” Where [0023] “The S-parameters may characterize electrical properties such as gain, return loss, voltage standing wave ratio (VSWR), reflection coefficient and amplifier stability.” And [0041] “As another example, calibration failures in a small frequency range (i.e., series of frequency responses) may indicate that coaxial cables 40 are loose. Complete failure across the entire frequency band (i.e., series of frequency responses) may indicate the presence of a more severe problem, such as one or more pins 34 and 36 sticking or breaking.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the electrical characteristics of the probe assembly of the test system and are expressed in phases or magnitudes over frequencies discussed in McCoy to the data verification test system in Tang for the purpose of being able to test certain ranges and phases of the signal depending on the type of circuit board undergoing testing This is advantageous because a measurement zone for s-parameters can obtain a start and stop window of frequencies where the values within the window can all be compared to the performance threshold of the s-parameters characterizing the signal as pass or fail, and complete failure across the entire frequency band may indicate the presence of a more severe problem, such as one or more pins sticking or breaking (e.g., [0038], [0041], McCoy).
Regarding Claim 6 and 12, Tang and McCoy teach the limitations of claim 4 and 10, respectively.
Tang further teaches wherein the two or more testing circuits are selected from a group essentially consisting an AIR testing circuit ([0023] “ Prior to testing an IC having unknown electrical properties (e.g., IC 206), a calibration procedure may be performed to determine electrical characteristics (and an error model) for testing system 200. VNA 208 is electrically connected to calibration standard 202 through ports 218, 220, cables 210, 212, and probes 214, 216. The tips of probes 214, 216 may be considered to define a "reference plane," which corresponds to a boundary between testing system 200 and calibration standard 202. VNA 208 may then provide excitation signals and may measure responsive signals, and may determine vector ratios of reflected or transmitted energy to energy incident upon calibration standard 202.”, testing done not on DUT, i.e., in air), an OPEN testing circuit, a SHORT testing circuit, a LOAD testing circuit, a THROUGH testing circuit and a LINE testing circuit ([0021] “Calibration standard 202 may be any one of a number of different types of calibration standards, including a thru-type (i.e., air is a thru in network analyzer calibration), line-type, short-type, open type and load-type calibration standard.”) and the measured uncorrected data is produced based on a corresponding standard measurement which is selected from an AIR standard ([0023] “ Prior to testing an IC having unknown electrical properties (e.g., IC 206), a calibration procedure may be performed to determine electrical characteristics (and an error model) for testing system 200. VNA 208 is electrically connected to calibration standard 202 through ports 218, 220, cables 210, 212, and probes 214, 216. The tips of probes 214, 216 may be considered to define a "reference plane," which corresponds to a boundary between testing system 200 and calibration standard 202. VNA 208 may then provide excitation signals and may measure responsive signals, and may determine vector ratios of reflected or transmitted energy to energy incident upon calibration standard 202.”, testing done not on DUT, i.e., in air), an OPEN standard, a SHORT standard, a LOAD standard, a THROUGH standard and a LINE standard ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) through one of the probes, and responsive signals are measured by the testing system through both probes (i.e., the measured uncorrected data is produced based on a corresponding standard measurement) .” Where [0021] “Calibration standard 202 may be any one of a number of different types of calibration standards, including a thru-type (i.e., air is a thru in network analyzer calibration), line-type, short-type, open type and load-type calibration standard.”).
Regarding Claim 7 and 18, Tang and McCoy teach the limitations of Claim 1 and 10, respectively
Tang further teaches inputting, via the probe assembly of the test system, the data to the calibration standard assembly ([0065] “In block 1004, the probe tips of probes (e.g., probes 214, 216, 314, 316, FIGS. 2, 3) (i.e., probe assembly data) are applied to (i.e., brought into contact with) the calibration standard (e.g., with probe contact areas 520, FIG. 5 of the calibration standard). In block 1006, excitation signals are provided by the testing system (e.g., by a VNA of the testing system) (i.e., incident data/signal from a main control unit) through one of the probes, and responsive signals are measured by the testing system through both probes.” Where [0064] “The method may begin, in block 1002, by providing one or more calibration standards ( e.g., calibration standards 400-404, 700-704, FIGS. 4, 7) (i.e., two or more testing circuits) that include end structures, in accordance with various embodiments previously described.”); repeatedly measuring uncorrected data through the two or more testing circuits of the calibration standard assembly ([0065] “Either way, blocks 1004-1008 may be repeated one or more additional times to determine one or more additional electrical parameters (e.g., additional S-parameters using the same calibration standard). In block 1009, a determination is made whether all calibration standards have been tested. If not, the process iterates as shown” where [0021] “Calibration standard 202 may be any one of a number of different types of calibration standards, including a thru-type (i.e., air is a thru in network analyzer calibration), line-type, short-type, open type and load-type calibration standard.”); and verifying repeatability of the measured uncorrected data by comparing a difference between any two of the repeatedly-measured uncorrected data ([0066] “In block 1010, calibration of the testing system is completed by generating an error model of the testing system ( e.g., by a processing system associated with the VNA or a separate computer) using the electrical parameters determined (i.e., electrical parameters like s-parameters measure the ratio of incident to reflected or transmitted power waves at its ports of each circuit) in blocks 1004-1009.”)
Tang does not teach a repeatability boundary setting.
McCoy teaches a repeatability boundary setting ([0034] To provide compliance boundaries (boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 8 and 19, Tang and McCoy teach the limitations of claim 1 and 10, respectively.
Tang further teaches wherein the main control unit includes a control host that calculates a compensation data for compensating measurement of the control host by comparing an ideal dataset with the verified measured uncorrected data ([0066] “In block 1010, calibration of the testing system is completed by generating an error model (i.e., compensation data) of the testing system ( e.g., by a processing system associated with the VNA or a separate computer (i.e., control host)) using the electrical parameters determined in blocks 1004-1009. The error model approximates the testing system's non-idealities (i.e., the testing system data is not ideal compared to the ideal data set). According to an embodiment, the error model may be based upon the use of S-parameter representations of network properties, for example, although the error model may be based on other representations, as well.”).
Regarding Claim 9 and 20, Tang and McCoy teach the limitations of claim 8 and 19 respectively.
Tang further teaches wherein the compensation data is provided for compensating a next measured uncorrected data so as to obtain an error term verification dataset ([0066] “In block 1010, calibration of the testing system is completed by generating an error model (i.e., error term verification) of the testing system ( e.g., by a processing system associated with the VNA or a separate computer) using the electrical parameters determined in blocks 1004-1009. The error model approximates the testing system's non-idealities. According to an embodiment, the error model may be based upon the use of S-parameter representations of network properties, for example, although the error model may be based on other representations, as well. The non-idealities represented in the error model may then be factored into future analyses performed by the testing system (i.e., compensating a next measured uncorrected data”); and the compensation data is verified if there is a difference between the error term verification dataset and the ideal dataset ([0066] “The error model approximates the testing system's non-idealities (i.e., different than the ideal data set). According to an embodiment, the error model may be based upon the use of S-parameter representations of network properties, for example, although the error model may be based on other representations, as well. The non-idealities represented in the error model may then be factored into future analyses performed by the testing system, to ensure that characteristics of a DUT with unknown characteristics are accurately measured.”)
Tang does not teach is within a model data boundary setting.
McCoy teaches is within a model data boundary setting ([0034] To provide compliance boundaries (boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database.” Where the boundary settings are modelled via [0035] “the upper and lower compliance variation limits for each S-parameter is calculated from the following two formulae:
Upper Compliance Limit=(BaselineUpper Limit+N)+(M×σ)+(P×λ×σ) (1)
Lower Compliance Limit=(Baseline Lower Limit−N)−(M×σ)−(P×λ×σ) (2)”)
Regarding Claim 11, Tang and McCoy teach the limitations of claim 10.
Tang does not teach wherein the verification boundary setting is adjustable and illustrated by a series of thresholds over frequencies or a range between an upper-limit line and a lower-limit line over frequencies.
McCoy teaches wherein the verification boundary setting is adjustable and illustrated by a series of thresholds over frequencies or a range between an upper-limit line and a lower-limit line over frequencies ([0037] “Adjustable parameter M is a multiplier of variance parameter σ that expands the upper and lower compliance limits by an amount based on the statistical variation of the verifications standard measurements in the verification standards database. That is, adjustable parameter M allows the user to adjust the pass/fail performance bounds by M times the baseline S-parameter variation in the verification standards database.” Where [0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 13, Tang and McCoy teach the limitations of claim 10.
Tang further teaches wherein, under a reflection mode, the analyzer processes signals received by at least one port via a signal terminal and a ground terminal of the at least one probe-head of the probe assembly ([0019] “A responsive, reflected signal (i.e., reflection mode) (b1) at the input port may then be measured (i.e., one port of signal), and the ratio of the reflected signal to the excitation signal may define the input reflection coefficient parameter (S 11 ).” Where [0047] More particularly, ground contact pads 482 of a device may be brought into contact with the outer conductive structures ( e.g., structures 461, 462, 464, 465) of a calibration standard, and signal pads 484 of a device may be brought into contact with the inner conductive structure(s) (e.g., structures 460, 463) of a calibration standard. Probes (e.g., probes 214, 216 or 314, 316, FIG. 2 or 3) of a testing system may then be brought into contact with probe contact areas of the inner and outer conductive structures, and the testing system may provide excitation signals to the device and measure responsive signals via the probes. When correlated with probe tips of a GSG probe ( e.g., probe tips 524 of probe 526, FIG. 5), the inner conductive structures (e.g., structures 410,440,443, 450, 460, 463, 470) may correspond with the signal bearing tip of the probe ( e.g., a central or "S" probe tip), and the first and second outer conductive structures (e.g., structures 411, 412, 441, 442, 444, 445, 451, 452, 461, 462, 464, 465, 471, 472) may correspond with the ground tips of the probe (e.g., the outer or "G" probe tips).”) ; and, under a transmission mode, the analyzer processes the signals received by two or more ports via signal terminals and ground terminals of the at least one probe-head of the probe assembly ([0019] “To measure the forward transmission gain parameter (S21), an excitation signal may be provided at the input port, and a responsive signal transmitted through the IC may be measured at the output port.” Where [0047] More particularly, ground contact pads 482 of a device may be brought into contact with the outer conductive structures ( e.g., structures 461, 462, 464, 465) of a calibration standard, and signal pads 484 of a device may be brought into contact with the inner conductive structure(s) (e.g., structures 460, 463) of a calibration standard. Probes (e.g., probes 214, 216 or 314, 316, FIG. 2 or 3) of a testing system may then be brought into contact with probe contact areas of the inner and outer conductive structures, and the testing system may provide excitation signals to the device and measure responsive signals via the probes. When correlated with probe tips of a GSG probe ( e.g., probe tips 524 of probe 526, FIG. 5), the inner conductive structures (e.g., structures 410,440,443, 450, 460, 463, 470) may correspond with the signal bearing tip of the probe ( e.g., a central or "S" probe tip), and the first and second outer conductive structures (e.g., structures 411, 412, 441, 442, 444, 445, 451, 452, 461, 462, 464, 465, 471, 472) may correspond with the ground tips of the probe (e.g., the outer or "G" probe tips).”).
Regarding Claim 15, Tang and McCoy teach the limitations of claim 14.
Tang does not teach wherein the series of frequency responses are expressed by a frequency response diagram displayed on a display device of the main control unit, and a verification boundary setting used to verify the measured uncorrected data is illustrated by a series of threshold as a boundary line shown in the frequency response diagram over frequencies or a range between an upper-limit line and a lower-limit line shown in the frequency response diagram over frequencies.
McCoy teaches wherein the series of frequency responses are expressed by a frequency response diagram displayed on a display device of the main control unit ([0048] “FIG. 4 is a diagrammatic view of a process for generating virtual models for use in a system-level simulation of a net 13. In the embodiment shown, the performance of driver 80 is measured to generate a virtual model of the system-level stimulus waveform”, where [0023] “In some embodiments, the electrical performance characteristics are stored in a Libra/Touchstone (available from Hewlett-Packard) compliant format. Network analyzer 18 (or a separate device) may then generate graphs, plots, and other data analysis based on the performance characteristics stored in data storage module 20.”), and a verification boundary setting used to verify the measured uncorrected data is illustrated by a series of threshold as a boundary line shown in the frequency response diagram over frequencies or a range between an upper-limit line and a lower-limit line shown in the frequency response diagram over frequencies ([0023] “In some embodiments, the electrical performance characteristics are stored in a Libra/Touchstone (available from Hewlett-Packard) compliant format. Network analyzer 18 (or a separate device) may then generate graphs, plots, and other data analysis based on the performance characteristics stored in data storage module 20.” See Fig 5, and [0034] To provide compliance boundaries (verification boundary settings) for future measurements of verification coupons 76, upper and lower compliance variation limits may be calculated from the verification standards database. A variety of techniques may be used to calculate the upper and lower variation limits from the verification standard S-parameters, such as Gaussian statistical analysis (using average and standard deviation), a National Institute of Standards and Technology (NIST) median absolute deviation (MAD) method, or NIST worst-case boundary curves. The upper and lower limits may be calculated for all S-parameter magnitude and phase values in the verification standards database. Once calculated, the upper and lower compliance variation limits indicate the type of variation expected in normal system calibrations and become the baseline standard (i.e., raw data boundary setting) by which future calibrations of printed wiring board test system 10 are judged.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 16, Tang and McCoy teach the limitations of claim 15.
Tang does not teach wherein the boundary line, the upper-limit line and/or the lower-limit line is adjustable via a computer-implemented adjustment tool on the frequency response diagram,
McCoy teaches wherein the boundary line, the upper-limit line and/or the lower-limit line is adjustable via a computer-implemented adjustment tool on the frequency response diagram ([0036] “To reduce the probability of calibration failures, it is generally desirable to judiciously widen the compliance limits whenever high accuracy is not needed. Thus, the upper and lower compliance limits may be further expanded by three adjustable parameters M, P, and N as in Equations 1 and 2. These parameters are adjustable by the user generating the verification standards database , depending on the level of accuracy desired in the calibration of printed wiring board test system 10.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Regarding Claim 17, Tang and McCoy teach the limitations of claim 16.
Tang does not teach wherein the boundary line, the upper-limit line and/or the lower-limit line has only one segment with a set of boundary values or has multiple segments with different sets of boundary values.
McCoy teaches wherein the boundary line, the upper-limit line and/or the lower-limit line has only one segment with a set of boundary values or has multiple segments with different sets of boundary values ([0056] “Eye diagram 108 includes vertical eye opening 110 measured at the center of the eye-opening relative to the horizontal axis, and horizontal eye opening 112 measured at about the zero-volt line along the vertical axis. It will be appreciated that the eye opening may be calculated different manners, and other metrics may be calculated from the eye opening, including jitter and amplitude noise. System-level compliance evaluation of net 13 may then be conducted by controller 16 by comparing vertical eye opening 110 to a performance threshold (i.e., lower limit boundary line value) stored in data storage module 20. After evaluating all nets 13 on printed wiring board 12, the performance of printed wiring board 12 may be categorized as passing or failing based on the comparison to the performance threshold. Printed wiring board 12 may alternatively or additionally be assigned to a performance rating group (e.g., Grade A, Grade B, etc.) based on a difference between vertical eye opening 110 and the performance threshold (i.e., multiple segments with different sets of lower limit boundary lines).”) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the boundary settings discussed in McCoy to the data verification test system in Tang for the purpose of having settings that mark the threshold limits of acceptable signal data. This is advantageous because when accurately testing defects in the transmission line, electronic components may be assembled onto a faulty printed wiring board can be caught saving time and money (e.g., [0005], McCoy).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Emma L. Alexander whose telephone number is (571)270-0323. The examiner can normally be reached Monday- Friday 8am-5pm EST.
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/EMMA ALEXANDER/Patent Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857