Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I drawn to a method, in the reply filed on 12/11/2025 is acknowledged.
Claims 12-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/11/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1).
Regarding Claim 1, Davis et al. teaches a method, comprising:
forming semiconductor dies 14 on a semiconductor wafer 10, the semiconductor dies 14 having a device side surface and having an opposing backside surface (Fig. 2A: 14, 10, Fig. 2B: 14, paragraph 0069, 0070);
forming a build-up routing layer 125, 135, 140, 130, 134, over the semiconductor wafer 10 by performing (see Fig. 2D-2F: 125, 140, 130, 134):
patterning connection level conductors 125 over the device side surface of the semiconductor dies 14 to form post connects 125 directly contacting the semiconductor dies 14 and extending to a distal end (Fig. 2C: 125, 14, paragraph 0073);
forming a first layer of dielectric material 130 over and surrounding the post connects 125 (Fig. 2D: 125, 130, paragraph 0074);
grinding the first layer of dielectric material 130 to expose the distal ends of the post connects 125 (Fig. 2E: 125, 130, paragraph 0076);
patterning trace level conductors 140 on the first layer of dielectric material 130, the trace level conductors 140 directly contacting distal ends of the post connects 125 (Fig. 2F: 135, 140, paragraph 0077);
depositing a second layer of dielectric material 134 over the connection level conductors 125 and the trace level conductors 140 (Fig. 2F: 134, 140, paragraph 0077);
and grinding the second dielectric layer 134 to expose a surface of the trace level conductors 140, portions of the exposed surface of a top layer of the trace level conductors 140 forming terminals 140 for semiconductor device packages (Fig. 2F: 140, 134, paragraph 0077);
cutting through the build-up routing layer 125, 135, 140, 130, 134, in scribe lanes 160 between the semiconductor dies 14 to form trenches extending into the semiconductor wafer 10 (Fig. 2M: 160, paragraph 0087) ;
Note that Fig. 2M is a zoomed in view of the build-up routing layer and does not show the semiconductor dies 14 and the semiconductor wafer 10.
Davis et al. fails to explicitly teach:
the semiconductor dies 14 having bond pads on a device side surface,
the post connects 125 directly contacting the bond pads of the semiconductor dies 14,
backgrinding the semiconductor wafer on the backside surface of the semiconductor wafer to form openings by exposing the trenches to separate the semiconductor dies from one another;
and covering a portion of the device side surface of the semiconductor dies, a portion of the build-up routing layer, and the openings between the semiconductor dies with mold compound, while the terminals formed of the trace level conductors are exposed from the mold compound.
However, Ory et al. teaches a method, comprising semiconductor dies 13 having bond pads 17 on a device side surface (Fig. 1: 13, 17, paragraph 0043).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. and Ory et al. in order to have the semiconductor dies have bond pads on a device side surface. Doing so would facilitate ease of electrical connection between the elements of the semiconductor dies and the build-up routing layer.
Further, when the bond pads of Ory et al. are disposed on the semiconductor dies of Davis et al., a person of ordinary skill in the art would have recognized that the post connects 125 would directly contact the bond pads of the semiconductor dies 14.
Ory et al. further teaches backgrinding the semiconductor wafer 11 on the backside surface of the semiconductor wafer 11 to form openings by exposing the trenches 21 to separate the semiconductor dies 13 from one another(Fig. 4-5: 21, 13, 11, paragraph 0062-0063).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. and Ory et al. in order to include a step of backgrinding the semiconductor wafer on the backside surface of the semiconductor wafer to form openings by exposing the trenches to separate the semiconductor dies from one another. Doing so would yield individualized semiconductor dies.
Furthermore, Liu et al. teaches a method, comprising covering a portion of the device side surface of the semiconductor dies 210, a portion of the build-up routing layer 206a, 206b, and the openings between the semiconductor dies 210 with mold compound 220, while the terminals formed of the trace level conductors are exposed from the mold compound 220 (Fig. 5: 206a, 206b, Fig. 9: 220, 210, Fig. 10: 220, paragraph 0044, 0046).
Note that the layers 206a, 206b are redistribution layers inherently comprising metal layers which are interpreted as the terminals formed of trace level interconnect.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al., Ory et al. and Liu et al. in order to have a step of covering a portion of the device side surface of the semiconductor dies, a portion of the build-up routing layer, and the openings between the semiconductor dies with mold compound, while the terminals formed of the trace level conductors are exposed from the mold compound. Doing so would encapsulate the semiconductor dies and enable the trace level conductors to be electrically connect to external circuits.
Regarding Claim 2, Liu et al. teaches the method of claim 1, and further comprising: cutting through the mold compound 220 between the semiconductor dies 210 along the trenches 228 to form separated semiconductor device packages (Fig. 11a-11B: 220, 210, 228, paragraph 0048).
Regarding Claim 6, Liu et al. teaches the method of claim 2, wherein the backside surface of the semiconductor dies 210 is covered with the mold compound 220 (see Fig. 10: 210, 220).
Regarding Claim 8, Davis et al. teaches the method of claim 1, wherein depositing the first layer of dielectric material 130 comprises depositing Ajinomoto build-up film (ABF), acrylonitrile butadiene styrene (ABS), acrylonitrile styrene acrylate (ASA), or epoxy resin (Fig. 2D: 130, paragraph 0074).
Regarding Claim 11, the combination of Davis et al. and Liu et al teaches, the method of claim 2, wherein the terminals (present in the RDL layers 206a, 206b of Fig. 13B of Liu et al.) have a planar surface on a board side surface, the mold compound 220 is formed with a planar surface and is coplanar with the terminals (as taught by Liu et al., see Fig. 13B), and the method forms a no-lead semiconductor device package (as taught by Davis et al. in paragraph 0003).
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1), as applied to Claim 2 above, further in view of Wang et al. (US 20240332135 A1).
Regarding Claim 3, the combination of Davis et al., Ory et al. and Liu et al. fails to teach the method of claim 2, and further comprising etching the mold compound to expose sides of the terminals from the mold compound.
However, Wang et al. teaches a method comprising etching the mold compound 86 to expose sides of the terminals 84 from the mold compound 86 (Fig. 12: 84, Fig. 86, Fig. 14, paragraph 0074).
Note that while in Fig. 14, the mold compound 86 is sawed through using saw 90, paragraph 0074 states that etching can be used instead to cut through the mold compound. Further note the side surfaces of the terminals 84 are exposed in Fig. 15 after the cutting process.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. with the teachings of Ory et al., Liu et al. and Wang et al. in order to have a step of etching the mold compound to expose sides of the terminals from the mold compound. Doing so would result in terminals with wettable flanks, as recognized by Wang et al. (paragraph 0074), thereby facilitating the attachment of the packages device to a next level of assembly.
Regarding Claim 5, Wang et al. teaches the method of claim 3, wherein the etching forms wettable flanks on the sides of the terminals 84 (Fig. 14, paragraph 0074).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1), further in view of Wang et al. (US 20240332135 A1), as applied to Claim 3 above, further in view of Kessler et al. (US 20170278762 A1).
Regarding Claim 4, the combination of Davis et al., Ory et al., Liu et al. and Wang et al. fails to teach the method of claim 3, wherein the etching forms non-wettable flanks on the sides of the terminals.
However, Kessler et al. teaches a method, wherein non-wettable flanks are formed on the sides of the terminal 2302 by introducing a non-wettable narrow gap 5000 formed in the mold compound 104 to prevent solder wetting within the gap (Fig. 50: 2302, 5000, 104, paragraph 0169, 0170).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. with the teachings of Ory et al., Liu et al., Wang et al. and Kessler et al. in order to have the etching step of Wang et al. be form non-wettable flanks on the sides of the terminals achieved by introducing a gap in the mold compound. Doing so would allow to precisely define and predict a flow path of the solder so that sufficient accumulation of solder material can be promoted at a desired location at which visual inspection is possible, as recognized by Kessler et al. (paragraph 0012).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1), as applied to Claim 2 above, further in view of Poddar et al. (US 20230136784 A1).
Regarding Claim 7, Liu et al. teaches the method of claim 2, wherein a portion of the backside surface 204 of the semiconductor dies 210 is exposed from the mold compound 220 (Fig. 12A: 210, 220, 204, paragraph 0049), except that it is done to form a thermal pad.
However, Poddar et al. teaches a method wherein a portion of the backside surface 524 of the semiconductor dies 505, 502 is exposed from the mold compound 503 to form a thermal pad 718 (Fig 7: 524, 505, 502, 503, paragraph 0047).
Note the die 505 together with the die pad 502 in Fig. 7 is interpreted as the semiconductor die. Further, the thermal pad 718 is not indexed in Fig. 7 but however is mentioned in paragraph 0047 as being on the circuit board 720 and soldered to the to the backside surface of the die 502, 505.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. with the teachings of Ory et al., Liu et al. and Poddar et al. in order to have a portion of the backside surface of the semiconductor dies exposed from the mold compound to form a thermal pad. Doing so would greatly increase the thermal performance of the package, as recognized by Arora et al. (paragraph 0047).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1), as applied to Claim 1 above, further in view of Tang et al. (US 20220344796 A1).
Regarding Claim 9, the combination of Davis et al., Ory et al. and Liu et al. fails to teach the method of claim 1, wherein patterning the connection level conductors 125 (Fig. 2E: 125 of Davis et al.) further comprises: depositing a seed layer over the device side surface of the semiconductor dies; patterning the seed layer using a photoresist and photolithography; and forming the connection level conductors using electroplating or electroless plating of copper, gold, nickel, palladium, tungsten, tin, silver, or combinations or alloys thereof.
However, Tang et al. teaches a method, wherein patterning the connection level conductors 214 further comprises: depositing a seed layer over the device side surface of the semiconductor dies 202; patterning the seed layer using a photoresist and photolithography; and forming the connection level conductors 214 using electroplating or electroless plating of copper, gold, nickel, palladium, tungsten, tin, silver, or combinations or alloys thereof (Fig. 2A-2B: 214, 202, paragraph 0045, 0046).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. with the teachings of Ory et al., Liu et al. and Tang et al. in order to have the step of patterning the connection level conductors further comprise: depositing a seed layer over the device side surface of the semiconductor dies; patterning the seed layer using a photoresist and photolithography; and forming the connection level conductors using electroplating or electroless plating of copper, gold, nickel, palladium, tungsten, tin, silver, or combinations or alloys thereof. Doing so would yield less material wastage as the seed layer ensures selective growth of material plating while the photoresist masks areas.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Davis et al. (US 20240030113 A1), in view of Ory et al. (US 20230021534 A1) and Liu et al. (US 20210159136 A1), as applied to Claim 2 above, further in view of Tang et al. (US 20220344796 A1).
Regarding Claim 10, the combination of Davis et al., Ory et al. and Liu et al. fails to teach the method of claim 2, wherein patterning the connection level conductors comprises: depositing a seed layer over the device side surface of the semiconductor dies; patterning the seed layer using photoresist and photolithography to expose the seed layer over the bond pads; forming the connection level conductors using electroplating or electroless plating of copper or copper alloy; and stripping the photoresist and removing any unused portions of the seed layer.
However, Tang et al. teaches a method, wherein patterning the connection level conductors 214 comprises: depositing a seed layer over the device side surface of the semiconductor dies 202; patterning the seed layer using photoresist and photolithography to expose the seed layer over the bond pads 208; forming the connection level conductors 214 using electroplating or electroless plating of copper or copper alloy; and stripping the photoresist and removing any unused portions of the seed layer (Fig. 2A-2B: 214, 202, paragraph 0045, 0046).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Davis et al. with the teachings of Ory et al., Liu et al. and Tang et al. in order to have the step of patterning the connection level conductors comprise: depositing a seed layer over the device side surface of the semiconductor dies; patterning the seed layer using photoresist and photolithography to expose the seed layer over the bond pads; forming the connection level conductors using electroplating or electroless plating of copper or copper alloy; and stripping the photoresist and removing any unused portions of the seed layer. Doing so would yield less material wastage as the seed layer ensures selective growth of material plating while the photoresist masks areas.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is (571) 272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 04/03/2025
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 9, 2026
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