DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 01/16/2026.
Applicant’s amendments filed 01/16/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 4-12, and 14-20; and cancellation of claims 2-3 and 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296309 to Chang et al. (hereinafter Chang) in view of Wang et al. (US 2018/0068998, hereinafter Wang).
With respect to claim 1, Chang discloses semiconductor structure (Chang, Fig. 1, ¶0002, ¶0017-¶0054), comprising:
a semiconductor substrate (50) (Chang, Fig. 1, insets 15-16, ¶0039, ¶0030, ¶0049);
a deep N-type well region (52) (Chang, Fig. 1, ¶0049) formed in the semiconductor substrate (50);
a first P-type well region (66, of the collector 71) (Chang, Fig. 1, ¶0043-¶0047) formed over the semiconductor substrate (50);
an N-type well region (77, of the base 72) (Chang, Fig. 1, ¶0043-¶0047) formed over the deep N-type well region (52), and surrounded by the first P-type well region (66);
a second P-type well region (66, of the emitter 73) (Chang, Fig. 1, ¶0043-¶0047) formed over the deep N-type well region (52), and surrounded by the N-type well region (77); and
a bipolar junction transistor (BJT) (Chang, Fig. 1, insets 15-16, ¶0042-¶0052), comprising:
a first active region of a collection region (71) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) formed over the first P-type well region (66), comprising a plurality of first fins (55) extending in a first direction (e.g., a vertical region, inset 15 of Fig. 1) and a plurality of first source/drain features (56) epitaxially grown on the plurality of first fins (55);
a second active region (e.g., on the left side of the emitter region 73) and a third active region (e.g., on the right side of the emitter region 73) of a base region (72) formed over the N-type well region (77), each comprising a plurality of second fins (57) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) extending in the first direction and a plurality of second source/drain features (58) epitaxially grown on the plurality of second fins (57); and
a fourth active region of an emitter region (73) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) formed over the second P-type well region (66), comprising a plurality of third fins (55) extending in the first direction and a plurality of third source/drain features (56) epitaxially grown on the plurality of third fins,
wherein the second active region and the third active region (fins 57 of the base 72) (Chang, Fig. 1, inset 15, ¶0042, ¶0046-¶0049) are disposed on opposite sides of the fourth active region (fins 55 of the emitter 73) in the first direction,
wherein in the first direction, the first active region (fins 55 of the collector 71) (Chang, Fig. 1, inset 15, ¶0042, ¶0046-¶0049) is longer than the fourth active region (fins 55 of the emitter 73).
Further, Chang does not specifically disclose that the fourth active region is longer than the second active region and the third active region, and wherein in the first direction, the second active region and the third active region are not disposed along the emitter region.
However, Wang teaches forming a bipolar junction transistor (BJT) (see the annotated Figs. 5 and 7 below) (Wang, Figs. 5, 7, ¶0003-¶0005, ¶0014-¶0016, ¶0026, ¶0028-¶0030), wherein in the first direction (D1), the fourth active region of the emitter region (R1) including first fins (F1) that are longer than second fins (F2) of the second active region and the third active region of the base region (R2), and the first active region of the collector region (R3) including fins (F3) is longer than the fourth active region of the emitter region (R1) including first fins (F1), and the second active region and the third active region (fins F2 of the base region R2) are not disposed along the emitter region (R1), to provide bipolar transistor with enhanced current gain and reduced device dimensions (Wang, Fig. 7, ¶0003-¶0005, ¶0030).
Specifically, Wang teaches (Wang, Fig. 7, ¶0028) that two base regions (R2) are disposed at two sides of the emitter region (R1) in the first direction (D1), respectively (see the annotated Fig. 7 of Wang below). Also, Fig. 5 of Wang shows a cross-sectional view along line D-D’ of Fig. 7, wherein fin (F2) of the base region (R2) is adjacent to the fin(F1) of the emitter region in the first direction D1, such that the second active region and the third active region including fins (F2) of the base region (R2) are not disposed along the emitter region (R1).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the fourth active region is longer than the second active region and the third active region, and wherein in the first direction, the second active region and the third active region are not disposed along the emitter region, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 4, Chang in view of Wang discloses the semiconductor structure as claimed in claim 1. Further, Chang does not specifically disclose the semiconductor structure, wherein in a second direction perpendicular to the first direction, a distance between the first active region and the second active region is equal to a distance between the first active region and the third active region.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT (Wang, Fig. 7, ¶0015, ¶0028), wherein in a second direction (D2) that is perpendicular to the first direction (D1), a distance between the first (e.g., the collector region R3) (Wang, Fig. 7, ¶0028) and fourth (e.g., the emitter region R1) active regions is equal to a distance between the first (e.g., the collector region R3) and second (e.g., the base region R2) active regions; wherein in the second direction (D2), the distance between the first (R3) and second (R2, on the left side of the emitter region) active regions is equal to a distance between the first (R3) and third (R2, on the right side of the emitter region) active regions, to provide bipolar transistor with enhanced current gain and reduced device dimensions (Wang, Fig. 7, ¶0003-¶0005, ¶0030).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein in a second direction perpendicular to the first direction, a distance between the first active region and the second active region is equal to a distance between the first active region and the third active region, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 5, Chang in view of Wang discloses the semiconductor structure as claimed in claim 1. Further, Chang discloses the semiconductor structure, wherein the plurality of first fins (55, of the collector) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) are longer than the plurality of third fins (55, of the emitter), but does not specifically disclose that the plurality of third fins are longer than the plurality of second fins.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT, wherein the first fins (F3, of the collector R3) are longer than the third fins (F1, of the emitter R1), and the third fins (F1, of the emitter R1) are longer than the second fins (F2) of the base (R2) (Wang, Fig. 7, ¶0015, ¶0028).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the plurality of third fins are longer than the plurality of second fins, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 7, Chang in view of Wang discloses the semiconductor structure as claimed in claim 1. Further, Chang discloses the semiconductor structure, wherein the BJT further comprises: a fifth active region (e.g., 71, on the right/left side of the emitter region 73) (Chang, Fig. 1, insets 15-16, ¶0042, ¶0046-¶0049) of the collection region (71) formed over the first P-type well region (66), comprising the plurality of first fins (55) extending in the first direction (e.g., the vertical direction in the Fig. 1, inset 15) and the plurality of first source/drain features (56) epitaxially grown on the plurality of first fins (55), wherein the first active region and the fifth active region are disposed on opposite sides of the fourth active region (e.g., the emitter region 73 including fins 55) in a second direction (e.g., a horizontal direction in the Fig. 1, inset 15) that is perpendicular to the first direction, wherein a number of the plurality of first fins (55) in the first active region (e.g., 71, on the left/right side of the emitter region 73) is equal to a number of the plurality of first fins (55) in the fifth active region (e.g., 71, on the right/left side of the emitter region 73).
Regarding claim 8, Chang in view of Wang discloses the semiconductor structure as claimed in claim 7. Further, Chang discloses the semiconductor structure, wherein the BJT further comprises: a sixth active region (e.g., 72, on the top side of the emitter 73, inset 15 of Fig. 1) (Chang, Fig. 1, insets 15-16, ¶0042, ¶0046-¶0049) and a seventh active region (e.g., 72, on the bottom side of the emitter 73, inset 15 of Fig. 1) of the base region (72) formed over the N-type well region (77), each comprising the plurality of second fins (57) and the plurality of second source/drain features (58) epitaxially grown on the plurality of second fins (57), wherein the sixth active region and the seventh active region are disposed on opposite sides (top and bottom) of the fourth active region (emitter region 73), but does not specifically disclose a sixth active region and a seventh active region of the base region, each comprising the plurality of second fins extending in the first direction, wherein the sixth active region and the seventh active region are disposed on opposite sides of the fourth active region in the first direction.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT, wherein a sixth active region (e.g., R2 region including two bottom fins F2 at the left side of the emitter region R1) (Wang, Fig. 7, ¶0015, ¶0028) and a seventh active region (e.g., R2 region including two bottom fins F2 at the right side of the emitter region R1) of the base region, each comprising the second fins (F2) extending in the first direction (D1), wherein the sixth and seventh active regions are disposed on opposite sides of the fourth active region (R1) in the first direction (D1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein a sixth active region and a seventh active region of the base region, each comprising the plurality of second fins extending in the first direction, wherein the sixth active region and the seventh active region are disposed on opposite sides of the fourth active region in the first direction, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 9, Chang in view of Wang discloses the semiconductor structure as claimed in claim 8. Further, Chang does not specifically disclose that the sixth active region is disposed between the second active region and the fifth active region, and the seventh active region is disposed between the third active region and the fifth active region, wherein the second active region, the third active region, the sixth active region, and the seventh active region have a same number of the plurality of second fins.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT, wherein the sixth active region (e.g., R2 region including two bottom fins F2 at the left side of the emitter region R1) (Wang, Fig. 7, ¶0015, ¶0028) is disposed between the second active region (e.g., R2 region including two top fins F2 at the left side of the emitter region R1) and the fifth active region (e.g., the collector region R3 at bottom side of the emitter region R1), and the seventh active region (e.g., R2 region including two bottom fins F2 at the right side of the emitter region R1) is disposed between the third active region (e.g., R2 region including two top fins F2 at the right side of the emitter region R1) and the fifth active region (e.g., the collector region R3 at bottom side of the emitter region R1), wherein the second, third, sixth, and seventh active regions have the same number of second fins (e.g., two fins F2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the sixth active region is disposed between the second active region and the fifth active region, and the seventh active region is disposed between the third active region and the fifth active region, wherein the second active region, the third active region, the sixth active region, and the seventh active region have a same number of the plurality of second fins, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 10, Chang in view of Wang discloses the semiconductor structure as claimed in claim 7. Further, Chang discloses the semiconductor structure, wherein the BJT further comprises: an eighth active region (e.g., two right/left fins 55 of the emitter 73) (Chang, Fig. 1, insets 15-16, ¶0042, ¶0046-¶0049) of the emitter region (73) formed over the second P-type well region (66), comprising the plurality of third fins (55) extending in the first direction (e.g., the vertical direction in Fig. 1, inset 15) ) and the plurality of third source/drain features (56) epitaxially grown on the plurality of third fins (55), but does not specifically disclose that the eighth active region is disposed between the fourth active region and the fifth active region, wherein a number of the plurality of third fins in the fourth active region is equal to a number of the plurality of third fins in the eighth active region.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT, wherein the eighth active region (e.g., R1 including two bottom fins F1 in Fig. 7) (Wang, Fig. 7, ¶0015, ¶0028) of the emitter region (R1) is disposed between the fourth active region (e.g., R1 including two top fins F1 of the emitter region R1 in Fig. 7) and the fifth active region (e.g., the collector region R3 at the bottom of the emitter region R1), wherein the number of the third fins (F1) in the fourth active region (e.g., two top fins F1 of the emitter region R1) is equal to the number of the third fins (F1) in the eighth active region (e.g., two bottom fins F1 of the emitter region R1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the eighth active region is disposed between the fourth active region and the fifth active region, wherein a number of the plurality of third fins in the fourth active region is equal to a number of the plurality of third fins in the eighth active region, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296309 to Chang in view of Wang (US 2018/0068998) as allied to claim 1, and further in view of Chang et al. (US Patent No. 9,035,426, hereinafter Chang’426).
Regarding claim 6, Chang in view of Wang discloses the semiconductor structure as claimed in claim 1. Further, Chang discloses the semiconductor structure, wherein a number of the plurality of second fins (e.g., two fins 57, of the base 72) (Chang, Fig. 1, insets 15-16, ¶0042, ¶0046-¶0049) is less than a number of the plurality of third fins (e.g., four fins 55, of the emitter region 73), but does not specifically disclose a number of the plurality of second fins is less than a number of the plurality of first fins.
However, Chan’426 teaches forming a BJT device, wherein the number (e.g., two base fins 22) (Chang’426, Figs. 1-2, Col. 3, lines 49-55) of the second fins (22) of the base region is less than the number (e.g., six collector fins 24) of the first fins, and the number of the second fins (e.g., two base fins 22) is less than the number (e.g., fifteen emitter fins 20) of the third fins (20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Wang by forming a plurality of collector fins and a plurality of base fins each having a specific number of fins as taught by Chang’426 to have the semiconductor structure, wherein a number of the plurality of second fins is less than a number of the plurality of first fins, in order to provide a BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
Claims 11-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296309 to Chang in view of Chang’426 (US Patent No. 9,035,426) and Wang (US 2018/0068998).
With respect to claim 11, Chang discloses semiconductor structure (Chang, Fig. 1, ¶0002, ¶0017-¶0054), comprising:
a semiconductor substrate (50) (Chang, Fig. 1, insets 15-16, ¶0039, ¶0030, ¶0049);
a deep N-type well region (52) (Chang, Fig. 1, ¶0049) formed in the semiconductor substrate (50);
a rectangular P-type well region (e.g., 66, for the emitter region 73) (Chang, Fig. 1, inset 15, ¶0042-¶0047) formed over the deep N-type well region (52);
a ring-shaped N-type well region (77, of the base 72) (Chang, Fig. 1, inset 15, ¶0042-¶0047) formed over the deep N-type well region (52), wherein the rectangular P-type well region (66, for the emitter region 73) is surrounded by the ring-shaped N-type well region (77);
a ring-shaped P-type well region (e.g., 66, for the collector region 71) (Chang, Fig. 1, inset 15, ¶0042-¶0047) formed over the semiconductor substrate (50), wherein the ring-shaped N-type well region (7) is surrounded by the ring-shaped P-type well region (66, for the collector region 71); and
a bipolar junction transistor (BJT) (Chang, Fig. 1, insets 15-16, ¶0042-¶0052), comprising:
a plurality of first active regions of a collection region (e.g., 71, on the right and left sides of the emitter region 73) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) formed over the ring-shaped P-type well region (66), each comprising a plurality of first fins (55) extending in a first direction (e.g., a vertical region, inset 15 of Fig. 1) and a plurality of first source/drain features (56) epitaxially grown on the plurality of first fins (55);
a plurality of second active regions of a base region (e.g., 72, on the right and left sides of the emitter region 73) formed over the ring-shaped N-type well region (77), each comprising a plurality of second fins (57) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) extending in the first direction and a plurality of second source/drain features (58) epitaxially grown on the plurality of second fins (57); and
a third active region of an emitter region (73) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) formed over the rectangular P-type well region (66), comprising a plurality of third fins (55) extending in the first direction and a plurality of third source/drain features (56) epitaxially grown on the plurality of third fins,
wherein in the first direction, the plurality of first active regions (fins 55 of the collector regions 71) (Chang, Fig. 1, inset 15, ¶0042, ¶0046-¶0049) are longer than the plurality of third active region (e.g., fins 55 of the emitter 73).
Further, Chang does not specifically disclose (1) a plurality of third active regions, each comprising a plurality of third fins extending in the first direction, (2) wherein the plurality of third active regions are longer than the plurality of second active regions, wherein in the first direction, the plurality of second active regions are not disposed along the emitter region.
Regarding (1), Chang ’426 teaches forming a bipolar junction transistor (BJT) (Chang’426, Figs. 1-2, Col. 2, lines 22-67; Col. 3, lines 1-55) comprising a plurality of third active regions of an emitter region separated by the isolation region (18), each of the plurality of third active region including a plurality of third fins (20) extending in the first direction (e.g., Y-direction in Figs. 1-2), to provide BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang by forming the emitter region including a plurality of fin regions of the BJT as taught by Chang’426 to have the semiconductor structure, comprising: a plurality of third active regions, each comprising a plurality of third fins extending in the first direction, in order to provide a BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
Regarding (2), Wang teaches forming a bipolar junction transistor (BJT) (see the annotated Figs. 5 and 7 of Wang above) (Wang, Fig. 7, ¶0003-¶0005, ¶0014-¶0016, ¶0026, ¶0028-¶0030), wherein in the first direction (D1), the third active region of the emitter region R1 including first fins F1 that are longer than second fins F2 of the second active regions of the base region R2, and the second active regions of the base region R2 are not formed between the emitter region R1 and the collector region R3 in a second direction (D2), such that the N-type well region (e.g., W1) between the first (collector region R3) and third (emitter region R1) active regions is free of the second active region (base region R2), to provide bipolar transistor with enhanced current gain and reduced device dimensions (Wang, Fig. 7, ¶0003-¶0005, ¶0030).
Specifically, Wang teaches (Wang, Fig. 7, ¶0028) that two base regions (R2) are disposed at two sides of the emitter region (R1) in the first direction (D1), respectively (see the annotated Fig. 7 of Wang below). Also, Fig. 5 of Wang shows a cross-sectional view along line D-D’ of Fig. 7, wherein fin (F2) of the base region (R2) is adjacent to the fin(F1) of the emitter region in the first direction D1, such that the second active region and the third active region including fins (F2) of the base region (R2) are not disposed along the emitter region (R1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the plurality of third active regions are longer than the plurality of second active regions, wherein in the first direction, the plurality of second active regions are not disposed along the emitter region, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claim 12, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang discloses the semiconductor structure, wherein the plurality of second active regions (e.g., the base regions 72 at the bottom and top region of the emitter region 73) (Chang, Fig. 1, insets 15-16, ¶0042, ¶0046-¶0049) are disposed on opposite sides of the plurality of third active regions (e.g., emitter region 73) in the first direction (e.g., a vertical direction in Fig. 1, inset 15).
Regarding claim 14, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang discloses the semiconductor structure, wherein the plurality of first fins (55, of the collector) (Chang, Fig. 1, insets 15-16, ¶0046-¶0049) are longer than the plurality of third fins (55, of the emitter), but does not specifically disclose that the plurality of third fins are longer than the plurality of second fins.
However, Wang teaches allocation design of the emitter region, the base region, and the collector region of the BJT, wherein the first fins (F3, of the collector R3) are longer than the third fins (F1, of the emitter R1), and the third fins (F1, of the emitter R1) are longer than the second fins (F2) of the base (R2) (Wang, Fig. 7, ¶0015, ¶0028).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by allocating the emitter region, the base region, and the collector region of the BJT as taught by Wang to have the semiconductor structure, wherein the plurality of third fins are longer than the plurality of second fins, in order to provide a bipolar transistor with enhanced current gain and reduced device dimensions (Wang, ¶0003-¶0005, ¶0030).
Regarding claims 15 and 16, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang does not specifically disclose that a number of the plurality of second fins in each of the plurality of second active regions is less than a number of the plurality of first fins in each of the plurality of first active regions (as claimed in claim 15); wherein a number of the plurality of second fins in each of the plurality of second active regions is less than a number of the plurality of third fins in each of the plurality of third active regions (as claimed in claim 16).
However, Chan’426 teaches forming a BJT device, wherein the number (e.g., two base fins 22) (Chang’426, Figs. 1-2, Col. 3, lines 49-55) of the second fins (22) of the base region in each of the second active regions is less than the number (e.g., six collector fins 24) of the first fins in each of the first active regions; and the number of the second fins (22) in each of the second active regions (base regions) is less than the number (e.g., fifteen emitter fins 20) of the third fins (20) in each of the third active regions (emitter regions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by forming a plurality of collector fins and a plurality of base fins each having a specific number of fins as taught by Chang’426 to have the semiconductor structure, wherein a number of the plurality of second fins in each of the plurality of second active regions is less than a number of the plurality of first fins in each of the plurality of first active regions (as claimed in claim 15); wherein a number of the plurality of second fins in each of the plurality of second active regions is less than a number of the plurality of third fins in each of the plurality of third active regions (as claimed in claim 16), in order to provide a BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
Regarding claim 17, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang does not specifically disclose that a number of the plurality of first fins in each of the plurality of first active regions is equal to a number of the plurality of third fins in each of the plurality of third active regions.
However, Chang’426 teaches forming a BJT device, wherein the number (e.g., six collector fins 24) of the first fins in each of the first active regions can be more or fewer and the number (e.g., fifteen) of the third fins (e.g., 20) in each of the third active regions (emitter regions) can be more or fewer (Chang’426, Figs. 1-2, Col. 3, lines 49-55).
Also, Chang’426 teaches that the effective fin junction area of the BJT depends on the number of fins, the length of the fins, and the width of the fins in the layout area (Chang’426, Figs. 1-2, Col. 4, lines 28-39).
Thus, Chang’426 recognizes that the number of fins and the length and the width of the fins impacts the effective fin junction area of the BJT. Thus, the number of fins and the length and the width of the fins are a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the number of fins and the length and the width of the fins as Chang’426 has identified the number of fins and the length and the width of the fins as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive specific number of fins of the collector and the emitter such that the number of the first fins in each of the first active regions is equal to the number of the third fins in each of the third active regions in order to provide the desired reduced effective fin junction area of the BJT as taught by Chang’426 (Col. 4, lines 28-39) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by optimizing the number of fins in the collector region and the emitter region as taught by Chang’426 to have the semiconductor structure, wherein a number of the plurality of first fins in each of the plurality of first active regions is equal to a number of the plurality of third fins in each of the plurality of third active regions, in order to provide a BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
Regarding claim 18, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang discloses the semiconductor structure, wherein the third active region (73) (Chang, Fig. 1, insets 15-16, ¶0042-¶0049) is disposed between the second active regions (72), and the second (72) and third active region (73) are disposed between the first active regions (71), but does not specifically disclose that the plurality of third active regions are disposed between the plurality of second active regions, and the plurality of second active regions and the plurality of third active regions are disposed between the plurality of first active regions.
However, Chang’426 teaches forming the third active regions (Chang’426, Figs. 1-2, Col. 3, lines 34-55), wherein the third active regions (e.g., emitter fins 20) are disposed between the second active regions (e.g., base fins 22), and the second and third active regions (e.g., fins 20 and 22) are disposed between the first active regions (e.g., collector fins 24).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by forming the plurality of emitter fins surrounded by the plurality of base fins and the plurality of collector fins as taught by Chang’426 to have the semiconductor structure, wherein the plurality of third active regions are disposed between the plurality of second active regions, and the plurality of second active regions and the plurality of third active regions are disposed between the plurality of first active regions, in order to provide a BJT device with improved overall performance and formed using FinFET process to increase the integration density of the integrated semiconductor device (Chang’426, Col. 1, lines 14-27; Col. 2, lines 22-26; Col. 3, lines 11-13).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296309 to Chang in view of Chang’426 (US Patent No. 9,035,426) and Wang (US 2018/0068998) as applied to claim 11, and further in view of Tseng (US 2017/0317197).
Regarding claim 19, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang does not specifically disclose that a number of the plurality of first active regions is equal to a number of the plurality of third active regions, and a number of the plurality of second active regions is greater than the number of the plurality of first active regions.
However, Tseng teaches forming a BJT device (Tseng, Figs. 3-4, ¶0006-¶0008, ¶0020-¶0024, ¶0026) having a layout including the bases and the collectors being disposed at different pair sides of the emitters, wherein the number (e.g., two) of the first active regions (e.g., collector regions 210C including at least a fin structure) (Tseng, Figs. 3-4, ¶0020-¶0024, ¶0026) is equal to the number (e.g., two) of the third active regions (e.g., E1 and E2 including emitter regions 210E having at least a fin structure), and the number (e.g., two base regions 210B on opposite sides of the first emitter E1, two base regions 210B on opposite sides of the second emitter E2, and the middle base region 212B) of the second active regions (e.g., base regions 210B including at least a fin structure) is greater than the number of the first active regions 210C), to provide improved BJT with reduced base area to increase current gain to improve performance (Tseng, Figs. 3-4, ¶0026).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by forming a BJT layout having the bases and the collectors being disposed at different pair sides of the emitters as taught by Tseng to have the semiconductor structure, wherein a number of the plurality of first active regions is equal to a number of the plurality of third active regions, and a number of the plurality of second active regions is greater than the number of the plurality of first active regions, in order to provide improved BJT with reduced base area to increase current gain to improve performance (Tseng, ¶0006-¶0008, ¶0026).
Regarding claim 20, Chang in view of Chang’426 and Wang discloses the semiconductor structure as claimed in claim 11. Further, Chang does not specifically disclose that a number of the plurality of second active regions is a sum of a number of the plurality of first active regions and a number of the plurality of third active regions.
However, Tseng teaches forming a BJT device (Tseng, Figs. 3-4, ¶0006-¶0008, ¶0020-¶0024, ¶0026) having a layout including the bases and the collectors being disposed at different pair sides of the emitters, wherein the number (e.g., two base regions 210B on opposite sides of the first emitter E1 and two base regions 210B on opposite sides of the second emitter E2) of the second active regions is the sum of the number of the first active regions (e.g., two collector regions 210C) and the number of the third active regions (e.g., two emitter regions E1 and E2), to provide improved BJT with reduced base area to increase current gain to improve performance (Tseng, Figs. 3-4, ¶0026).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chang/Chang’426/Wang by forming a BJT layout having the bases and the collectors being disposed at different pair sides of the emitter as taught by Tseng to have the semiconductor structure, wherein a number of the plurality of second active regions is a sum of a number of the plurality of first active regions and a number of the plurality of third active regions, in order to provide improved BJT with reduced base area to increase current gain to improve performance (Tseng, ¶0006-¶0008, ¶0026).
Response to Arguments
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument that “[i]n FIG. 7…of Wang, in the alleged first direction (the direction in which the alleged first/second/third fins extended), the alleged second fins (F2) are disposed along the alleged third fins (F1). That is, the alleged second fins (F2) are disposed along the alleged emitter region (R1)”, the examiner submits that Fig. 7 of Wang (see the annotated Figs. 5 and 7 of Wang above) shows that two base regions (R2) are disposed at two sides of the emitter region (R1) in the first direction (D1), respectively (see the annotated Fig. 7 of Wang above). Also, Fig. 5 of Wang (see the annotated Fig. 5 above) shows a cross-sectional view along line D-D’ of Fig. 7, wherein fin (F2) of the base region (R2) is adjacent to the fin(F1) of the emitter region in the first direction D1, such that the second active region and the third active region including fins (F2) of the base region (R2) are not disposed along the emitter region (R1), as required by claim 1. Thus, the above applicant’s arguments are not persuasive, and the rejections of claim 1 and 11 under 35 USC 103 over Chang in view of Wang are maintained.
Regarding dependent claims 4-10, 12, and 14-20 which depend on the independent claims 1 and 11, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891