Detailed Action
This office action is in response to the amendment filed on March 30th, 2026. Claims 1-20 are pending. Claim 13 has been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed March 30th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 9-12, “Remarks”) that Bussing and the other cited references fail to teach the limitations presented in amended Claims 1, 11 and 16.
However, as seen below, Claims 1, 11, and 16 are now rejected by the combination of Bussing, Pressel, and Chen.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-3, 6-11, 14-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bussing et al. (2018/0306843 A1; hereinafter Bussing) in view of Pressel et al. (2010/0019370 A1; hereinafter Pressel) and Chen et al. (2018/0102298 A1; hereinafter Chen).
Regarding Claim 1, Bussing (figs. 7-7A) teaches a sensor ([0115], 700) comprising:
a wafer level package subcomponent (700) comprising: a semiconductor integrated circuit ([0115], 708) comprising an active side ([0115], 708a),
the active side (708a) comprising at least one magnetic sensor ([0115], any one of 710a-710n) and at least one contact pad; and
a housing ([0119], 716) comprising material including mold compound ([0119], 716 is defined as mold material) embedding and overmolding (716 extends around all of 708) the semiconductor integrated circuit (708) arranged for allowing electric connection ([0117]-[0118], solder bumps connect to leads carrying low voltage current) to the at least one contact pad of the active side (708a) of the semiconductor integrated circuit (708), the housing (716) having a first side at the active side (716 by 708a) and a second side opposite to the active side (716 by 708b), the second side comprising material including mold compound ([0119], 716 is defined as mold material) and forming a backside of the wafer level package subcomponent (top surface of 700);
a primary leadframe ([0115], 706b); and
a set of electric contacts ([0118], portion of leads 706a positioned below 720a-720n) for signal interchange ([0117]-[0118]); wherein
the active side (708a) of the semiconductor integrated circuit (708) faces the primary leadframe (706b), the semiconductor integrated circuit (708) being electrically isolated from the primary leadframe (706b), the at least one contact pad of the semiconductor integrated circuit (708) further being electrically connected to electric contacts of the set (portion of leads 706a positioned below 720a-720n), for transferring measurement signals to a secondary leadframe ([0115], 706a), wherein
the wafer level package subcomponent including at least the housing and the semiconductor integrated circuit is entirely encapsulated in a further standard package..
Bussing doesn’t explicitly teach the active side comprising at least one contact pad, while Bussing does teach electrical connection ([0116]-[0118]) to the active side (708a) of the semiconductor integrated circuit (708).
However, Pressel (fig. 4B) teaches the active side ([0026], bottom of 10) comprising at least one contact pad ([0026], 24) while yielding the predictable result of providing electrical connection to a semiconductor integrated circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the contact pad of Pressel for the undisclosed means of electrical connection of Bussing, since simple substitution electrical contacts for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Bussing doesn’t teach the wafer level package subcomponent including at least the housing and the semiconductor integrated circuit is entirely encapsulated in a further standard package.
However, Chen (fig. 7) teaches the wafer level package subcomponent ([0065], 130, 620) including at least the housing (620) and the semiconductor integrated circuit (130) is entirely encapsulated in a further standard package ([0067], 630 entirely encapsulates 620, see fig. 7). Chen also teaches that package-on-package is a cost-effective solution to high-density system integration in a single package ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the package-on-package assembly of Chen to provide higher densities in a single package.
Regarding Claim 2, Bussing doesn’t teach the sensor according to claim 1, further comprising a redistribution layer for electrically connecting the at least one contact pad to the electric contacts of the set, the redistribution layer embedded in the further standard package.
However, Pressel (fig. 3I) teaches a redistribution layer ([0031], 27) for electrically connecting the at least one contact pad (24, see fig. 3F) to the electric contacts of the set ([0034], 32). Pressel also teaches the redistribution later provides electrical contact to components outside the device according to geometric needs ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the redistribution layer of Pressel to provide electrical contact according to geometric needs.
Furthermore, Chen (fig. 6) teaches the redistribution layer ([0065], 423) embedded in the further standard package (202).
Regarding Claim 3, Pressel (figs. 3F and 3H) teaches the sensor according to claim 2, wherein the redistribution layer (27) comprises a conductive track ([0032], 12, 28).
Regarding Claim 6, Bussing (fig. 7) teaches the sensor according to claim 1, wherein the sensor comprises a further circuit (a different one of 710a-710n) embedded in the housing (716) and directly or indirectly electrically connected to set of electric contacts (portion of leads 706a positioned below 720a-720n).
Regarding Claim 7, Bussing (fig. 7) teaches the sensor according to claim 6, wherein the further circuit (a different one of 710a-710n) comprises a III- V semiconductor circuit ([0057], may be GaAs).
Regarding Claim 8, Bussing doesn’t teach the sensor according to claim 6, wherein the further circuit is electrically connected to the semiconductor integrated circuit by a redistribution layer.
However, Pressel (figs. 3B and 3I) teaches the further circuit ([0024], 22) is electrically connected to the semiconductor integrated circuit ([0024], 10) by a redistribution layer ([0031], 27). Pressel also teaches the redistribution later provides electrical contact to components outside the device according to geometric needs ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the redistribution layer of Pressel and replacing the further circuit of Bussing with the further circuit of Pressel to provide electrical contact according to geometric needs.
Regarding Claim 9, the combination of Bussing (fig. 7), Pressel (fig. 4B), and Chen (fig. 7) teaches the sensor according to claim 1, further comprising a solder bump (Bussing, [0118], 720a-720n) for electrically connecting the at least one contact pad (Pressel, 24) to the electric contacts of the set (Bussing, portion of leads 706a positioned below 720a-720n) the solder bump (Bussing, 720a-720n) entirely encapsulated (the housing 716 of Bussing encapsulates the solder bumps 720a-720n which is further encapsulated by the further packaging 630 of Chen) against the electric contacts of the set (Bussing, portion of leads 706a positioned below 720a-720n) by the further standard package (Chen, 630).
Regarding Claim 10, Pressel (figs. 3F, 3H, and 3I) teaches the sensor according to claim 9, wherein the redistribution layer (27, see fig. 3I) comprises a conductive track ([0032], 12, 28, see figs. 3F and 3H) arranged between the at least one contact pad (24, see fig. 3F) and the solder bump ([0048], 34 may be deposited against 32, see fig. 4B).
Regarding Claim 11, Bussing (fig. 7) teaches a sensor ([0115], 700) comprising:
a leadframe ([0115], 706a, 706b) comprising a set of electric contacts (portion of leads 706a positioned below 720a-720n);
a wafer level package subcomponent (700) comprising: a semiconductor integrated circuit ([0115], 708) for sensing electric currents comprising an active side ([0115], 708a),
the active side (708a) comprising at least one magnetic sensor ([0115], 710a-710n) and at least one contact pad and
a housing ([0119], 716) comprising material including mold compound ([0119]) embedding and overmolding (716 extends around all of 708) the semiconductor integrated circuit (708) arranged for allowing electric connection ([0117]-[0118], solder bumps connect to leads carrying low voltage current) to the at least one contact pad of the active side (708a) of the semiconductor integrated circuit (708),
the housing (716) having a first side at the active side (716 by 708a) and a second side opposite to the active side (716 by 708b), the second side comprising material including mold compound ([0119], 716 is defined as mold material) and forming a backside of the wafer level package subcomponent (top surface of 700);
a redistribution layer electrically connecting the at least one contact pad to the set of electric contacts, the redistribution layer comprising a conductive track; and
an isolation layer on the redistribution layer; and
a standard package assembling the wafer level package subcomponent, the standard package embedding at least the housing and the redistribution layer.
Bussing doesn’t explicitly teach the active side comprising at least one contact pad, while Bussing does teach electrical connection ([0116]-[0118]) to the active side (708a) of the semiconductor integrated circuit (708).
However, Pressel (fig. 4B) teaches the active side ([0026], bottom of 10) comprising at least one contact pad ([0026], 24) while yielding the predictable result of providing electrical connection to a semiconductor integrated circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the contact pad of Pressel for the undisclosed means of electrical connection of Bussing, since simple substitution electrical contacts for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Bussing doesn’t teach a redistribution layer electrically connecting the at least one contact pad to the set of electric contacts, the redistribution layer comprising a conductive track; and an isolation layer on the redistribution layer.
However, Pressel (figs. 3F, 3H, and 3I) teaches a redistribution layer ([0031], 27, see 3I) electrically connecting the at least one contact pad (24, see fig. 3F) to the electric contacts of the set ([0034], 32), the redistribution layer (27) comprising a conductive track ([0032], 12, 28); and an isolation layer ([0032], 29, 30, 31) on the redistribution layer (27). Pressel also teaches the redistribution later provides electrical contact to components outside the device according to geometric needs ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the redistribution layer of Pressel to provide electrical contact according to geometric needs.
Bussing doesn’t teach a standard package assembling the wafer level package subcomponent, the standard package embedding at least the housing and the redistribution layer.
However, Chen (fig. 7) teaches a standard package ([0067], 630 entirely encapsulates 620, see fig. 7) assembling the wafer level package subcomponent ([0065], 130, 423, 620, see figs. 6-7), the standard package (630) embedding at least the housing (620) and the redistribution layer (423). Chen also teaches that package-on-package is a cost-effective solution to high-density system integration in a single package ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the package-on-package assembly of Chen to provide higher densities in a single package.
Regarding Claim 14, Bussing (fig. 7) teaches the sensor according to claim 11, wherein the sensor comprises a further circuit (a different one of 710a-710n) embedded in the wafer level package subcomponent (700) and electrically connected to the semiconductor integrated circuit (708).
Regarding Claim 15, Pressel (figs. 3B, 3F, and 3H) teaches the sensor according to claim 11, wherein the conductive track (12, 28) is distal (12 and 28 extend away from chips 10 and 22) from the at least one magnetic sensor ([0014], [0020], 10, 22).
Regarding Claim 16, Bussing (fig. 7) teaches a current sensor ([0115], 700) configured to sense a current through a current conductor ([0116], conductor), the sensor (700) comprising:
a leadframe ([0115], 706a, 706b) comprising a set of electric contacts (portion of leads 706a positioned below 720a-720n);
a wafer level package subcomponent (700) comprising: a semiconductor integrated circuit ([0115], 708) for sensing electric currents comprising an active side ([0115], 708a),
the active side (708a) comprising at least one magnetic sensor ([0115], 710a-710n) and at least one contact pad and
a housing ([0119], 716) comprising material including mold compound ([0119]) embedding and overmolding (716 extends around all of 708) the semiconductor integrated circuit (708) arranged for allowing electric connection ([0117]-[0118], solder bumps connect to leads carrying low voltage current) to the at least one contact pad of the active side (708a) of the semiconductor integrated circuit (708),
the housing (716) having a first side at the active side (716 by 708a) and a second side opposite to the active side (716 by 708b), the second side comprising material including mold compound ([0119], 716 is defined as mold material) and forming a backside of the wafer level package subcomponent (top surface of 700);
a redistribution layer electrically connecting the at least one contact pad to the set of electric contacts via a solder bump, the redistribution layer comprising a conductive track, the conductive track arranged between the at least one contact pad and the solder bump; and
an isolation layer on the redistribution layer, wherein
the wafer level package subcomponent is assembled in a further standard package, the further standard package embedding at least the housing, the redistribution layer, and the isolation layer.
Bussing doesn’t explicitly teach the active side comprising at least one contact pad, while Bussing does teach electrical connection ([0116]-[0118]) to the active side (708a) of the semiconductor integrated circuit (708).
However, Pressel (fig. 4B) teaches the active side ([0026], bottom of 10) comprising at least one contact pad ([0026], 24) while yielding the predictable result of providing electrical connection to a semiconductor integrated circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the contact pad of Pressel for the undisclosed means of electrical connection of Bussing, since simple substitution electrical contacts for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Bussing doesn’t teach a redistribution layer electrically connecting the at least one contact pad to the set of electric contacts via a solder bump, the redistribution layer comprising a conductive track, the conductive track arranged between the at least one contact pad and the solder bump; and an isolation layer on the redistribution layer
However, Pressel (figs. 3F, 3H, and 3I) teaches a redistribution layer ([0031], 27, see 3I) electrically connecting the at least one contact pad (24, see fig. 3F) to the electric contacts of the set ([0045], 25) via a solder bump ([0048], 34), the redistribution layer (27) comprising a conductive track ([0032], 12, 28), the conductive track (12, 28) arranged between the at least one contact pad (24) and the solder bump (34); and an isolation layer ([0032], 29, 30, 31, see fig. 3I) on the redistribution layer (27). Pressel also teaches the redistribution later provides electrical contact to components outside the device according to geometric needs ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the redistribution layer of Pressel to provide electrical contact according to geometric needs.
Bussing doesn’t teach the wafer level package subcomponent is assembled in a further standard package, the further standard package embedding at least the housing, the redistribution layer, and the isolation layer.
However, Chen (fig. 7) teaches the wafer level package subcomponent ([0065], 130, 423, 620, see figs. 6-7) is assembled in a further standard package ([0067], 630 entirely encapsulates 620, see fig. 7), the further standard package (630) embedding at least the housing (620), the redistribution layer ([0056], 4232, see fig. 6), and the isolation layer ([0056], 4233, see fig. 6). Chen also teaches that package-on-package is a cost-effective solution to high-density system integration in a single package ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the package-on-package assembly of Chen to provide higher densities in a single package.
Regarding Claim 18, Bussing (fig. 7) teaches the sensor according to claim 16, wherein the sensor comprises a further circuit (a different one of 710a-710n) embedded in the wafer level package subcomponent (700) and electrically connected to the semiconductor integrated circuit (708).
Regarding Claim 19, Bussing (fig. 7) teaches the sensor according to claim 18, wherein the further circuit is electrically connected to the semiconductor integrated circuit by a redistribution layer.
However, Pressel (figs. 3B and 3I) teaches the further circuit ([0024], 22) is electrically connected to the semiconductor integrated circuit ([0024], 10) by a redistribution layer ([0031], 27). Pressel also teaches the redistribution later provides electrical contact to components outside the device according to geometric needs ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the redistribution layer of Pressel and replacing the further circuit of Bussing with the further circuit of Pressel to provide electrical contact according to geometric needs.
Regarding Claim 20, Pressel (figs. 3B, 3F, and 3H) teaches the sensor according to claim 16, wherein the conductive track (12, 28) is distal (12 and 28 extend away from chips 10 and 22) from the at least one magnetic sensor ([0014], [0020], 10, 22).
Claims 4-5, 12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bussing, Pressel, and Chen as applied to Claims 1, 11, and 16 above, and further in view of Racz et al. (2014/0253103 A1; hereinafter Racz).
Regarding Claim 4, Bussing doesn’t teach the sensor according to claim 1, further comprising isolation material between the active side and the primary leadframe, while Bussing does teach the active side (708a) and the primary leadframe (706b) may be electrically isolated ([0117]).
Racz (figs. 1-2) teaches isolation material ([0032], 15, see fig. 2) between the active side ([0029], top of 1, see fig. 2) and the primary leadframe ([0027], 4, 5, 6, 8). Racz also teaches that this isolation structure achieves the required dielectric strength between the adjacent conductive portions ([0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the isolation layer of Racz to achieve required dielectric strength.
Regarding Claim 5, Racz (fig. 2) teaches the sensor according to claim 4, wherein the isolation material comprises polyimide ([0032], polyimide).
Regarding Claim 12, Bussing doesn’t teach the sensor according to claim 11, wherein the isolation layer comprises polyimide.
Racz (fig. 2) teaches the isolation layer ([0032], 15) comprises polyimide ([0032], polyimide). Racz also teaches that this isolation structure achieves the required dielectric strength between the adjacent conductive portions ([0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the isolation layer of Racz to achieve required dielectric strength.
Regarding Claim 17, Bussing doesn’t teach the sensor according to claim 16, wherein the isolation layer comprises polyimide.
Racz (fig. 2) teaches the isolation layer ([0032], 15) comprises polyimide ([0032], polyimide). Racz also teaches that this isolation structure achieves the required dielectric strength between the adjacent conductive portions ([0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the sensor of Bussing to include the isolation layer of Racz to achieve required dielectric strength.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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