DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I and Species (d), (claims 1 and 6-13), in the
reply filed on 01/06/2026 is acknowledged. Non-elected claims 2-5 and 14-20 were withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, it recites the limitation “wherein the wet oxidation process is performed at a temperature of about 800 ℃ or less and is performed at a temperature of about 700 ℃ to about 800 ℃”. It is not clear what range of the temperature is claimed. Therefore, it is indefinite. For the examination purpose, the limitation “wherein the wet oxidation process is performed at a temperature of about 800 ℃ or less and is performed at a temperature of about 700 ℃ to about 800 ℃” is interpreted as two optional ranges of temperatures.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20180301564 A1) in view of Chang (US 20230118990 A1, hereinafter Chang).
Re: Independent Claim 1, Kwon discloses a method of manufacturing a semiconductor device (Fig. 18A), the method comprising:
PNG
media_image1.png
380
430
media_image1.png
Greyscale
Kwon’s Figure 6A-Annotated.
forming alternating layers (110-120 sacrificial semiconductor layers 110 and channel semiconductor layers 120 may be alternately and repeatedly stacked on a substrate 100 in [0045], Fig. 4A-B), where a silicon germanium layer (110 made of SiGe in [0045], Fig. 4A) and a silicon layer (120 made of Si in [0045], Fig. 4A) are alternately stacked, on a substrate (100 substrate in [0029], Fig. 4A);
patterning and etching (the sacrificial semiconductor layers 110 and the channel semiconductor layers 120 may be patterned to form preliminary channel stacks pCS formed by 111 and 121 in [0047], Fig. 5B) the alternating layers (110-120) to form a fin structure (pCS-111-121 in [0047], Fig. 5B) protruding onto the substrate (100), and then, forming a silicon nitride film (102 liner layer made of SiN in [0048], Fig. 5A-B) on a surface and a sidewall of each of the alternating layers having the fin structure (pCS-111-121, Fig. 5B);
sequentially forming a dummy gate (134 sacrificial gate pattern in [0049], Fig. 6A-B) and a film (136 gate mask pattern in [0049], Fig. 6A-B) on the alternating layers (pCS) with the silicon nitride film (102) therebetween, and then, forming a gate spacer (140 gate spacer layer in [0051], Fig. 6A) on a sidewall of the dummy gate (134);
PNG
media_image2.png
400
464
media_image2.png
Greyscale
Kwon’s Figure 7A-Annotated.
etching (the gate spacer layer 140 is partially removed, then lateral regions of the liner layer 102 are exposed then this are removed in [0053], Fig. 7A) the silicon nitride film (102) upward exposed, and then, etching (the pCs are etched resulting in channel stacks CS in [0053], Fig. 7A) the alternating layers (pCS) by using the film (136) as a hard mask (136 is gate mask pattern in [0049], Fig. 7A); and
selectively (an etch selectivity to the sacrificial semiconductor patterns 112 in [0054], Fig. 8A) forming an inner spacer (146 inner spacers in [0055], Fig. 9A) in a sidewall of each of silicon germanium layers (110 correspond to 112 in Fig. 9A) among the silicon germanium layers (112 in Fig. 9A) and silicon layers (120 correspond to 122 in Fig. 9A) of the etched alternating layers (CS in [0053], Fig. 7A).
Kwon does not expressly disclose a film on the alternating layers made of silicon oxide.
However, in the same semiconductor device manufacturing field of endeavor, Chang discloses a silicon oxide film (126a as part of the hard mask layer 126 in [0026], Fig. 6) on the alternating layers (112 nanosheet stacks in [0026], Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chang’s method of a silicon oxide film on the alternating layers to Kwon’s method to pattern the nanosheets stacks ([0026], Chang).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20180301564 A1) in view of Chang (US 20230118990 A1, hereinafter Chang) and further in view of Chen et al. (US 12317540 B2, hereinafter Chen).
Re: Claim 6, Kwon modified by Chang discloses method of claim 1,
Kwon modified by Chang does not expressly disclose wherein the forming of the inner spacer comprises: forming a silicon oxide film on the sidewall of each of the silicon germanium layers and the silicon layers of the etched alternating layers; etching the silicon oxide film until the sidewalls of the silicon layers are exposed; and forming, as the inner spacer, the silicon oxide film remaining on the sidewalls of the silicon germanium layers in a state where the sidewalls of the silicon layers are exposed.
However, in the same semiconductor device manufacturing field of endeavor, Chen discloses wherein the forming of the inner spacer (140 inner spacer in Col. 8, lines 11-12, Fig. 2E-1) comprises: forming a silicon oxide film (138 inner spacer layer made of SiO2 in Col. 8, lines 3-4, Fig. 2D-1) on the sidewall (having a width on 106 different to a width on 108 Fig. 2D-1) of each of the silicon germanium layers (106 made of SiGe in Col. 4, lines 55-59, Fig. 2D-1) and the silicon layers (108 made of Si in Col. 4, lines 55-59, Fig. 2D-1) of the etched alternating layers (106-108 Fig. 2D-1); etching (in Col. 8, lines 11-13, Fig. 2E-1) the silicon oxide film (138) until the sidewalls of the silicon layers (108) are exposed (Fig. 2E-1); and forming, as the inner spacer (140), the silicon oxide film (138) remaining (Fig. 2E-1) on the sidewalls of the silicon germanium layers (108) in a state where the sidewalls of the silicon layers (108) are exposed (Fig. 2E-1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chen’s method of wherein the forming of the inner spacer comprises: forming a silicon oxide film on the sidewall of each of the silicon germanium layers and the silicon layers of the etched alternating layers; etching the silicon oxide film until the sidewalls of the silicon layers are exposed; and forming, as the inner spacer, the silicon oxide film remaining on the sidewalls of the silicon germanium layers in a state where the sidewalls of the silicon layers are exposed to the combination of Kwon and Chang to separate the source/drain structures and the gate structures formed in subsequent manufacturing processes (Col. 8, lines 16-18, Chen).
Claim(s) 7-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20180301564 A1) in view of Chang (US 20230118990 A1, hereinafter Chang), in view of Chen et al. (US 12317540 B2, hereinafter Chen) and further in view of Frougier et al. (US 20190378915 A1, hereinafter Frougier).
Re: Claim 7, Kwon modified by Chang and Chen discloses the method of claim 6, wherein the forming of the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) comprises growing the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) on the sidewall of each of the silicon germanium layers (112 in Fig. 7A, Kwon) and the silicon layers (122 in Fig. 7A).
Kwon modified by Chang and Chen does not expressly disclose wherein the forming of the silicon oxide film by using a thermal oxidation process.
However, in the same semiconductor device manufacturing field of endeavor, Frougier discloses wherein the forming of the silicon oxide film by using a thermal oxidation process (a wet oxidation as an example of a thermal oxidation conducted at 625 degrees C in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Frougier’s method of wherein the forming of the silicon oxide film by using a thermal oxidation process to the combination of Kwon, Chang and Chen to form inner spacers ([0047], Frougier).
Re: Claim 8, Kwon modified by Chang and Chen discloses the method of claim 6, wherein the forming of the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) comprises growing the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) on the sidewall of each of the silicon germanium layers (112 in Fig. 7A, Kwon) and the silicon layers (122 in Fig. 7A).
Kwon modified by Chang and Chen does not expressly disclose wherein the forming of the silicon oxide film by using a wet oxidation process.
However, in the same semiconductor device manufacturing field of endeavor, Frougier discloses wherein the forming of the silicon oxide film by using a wet oxidation process (a wet oxidation conducted at 625 degrees C in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Frougier’s method of wherein the forming of the silicon oxide film by using a wet oxidation process to the combination of Kwon, Chang and Chen to form inner spacers ([0047], Frougier).
Re: Claim 9, Kwon modified by Chang, Chen and Frougier discloses the method of claim 8, wherein the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) formed on the sidewall of each of the silicon germanium layers is grown to have a first width (having a width on 106 different to a width on 108 Fig. 2D-1) in a center direction of the silicon germanium layers (112 in Fig. 7A, Kwon), and the silicon oxide film (138 Fig. 2D-1, from Chen applied to Kwon) formed on the sidewall of each of the silicon layers (122 in Fig. 7A) is grown to have a second width (having a width on 106 different to a width on 108 Fig. 2D-1) in a center direction of the silicon layers (122 in Fig. 7A).
Re: Claim 10, Kwon modified by Chang, Chen and Frougier discloses the method of claim 8, wherein the wet oxidation process (a wet oxidation conducted at 625 degrees C in [0047], Frougier) is performed at a temperature of about 800 ℃ or less (625 degrees C in [0047], Frougier) and is performed at a temperature of about 700 ℃ to about 800 ℃.
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 20180301564 A1) in view of Chang (US 20230118990 A1, hereinafter Chang), in view of Chen et al. (US 12317540 B2, hereinafter Chen) and further in view of Frougier et al. (US 20190378915 A1, hereinafter Frougier) and further in view of Wang et al. (US 20200168742 A1, hereinafter Wang).
Re: Claim 11, Kwon modified by Chang and Chen discloses the method of claim 6,
Kwon modified by Chang and Chen does not expressly disclose wherein the etching of the silicon oxide film comprises etching the silicon oxide film by using a wet etching process.
However, in the same semiconductor device manufacturing field of endeavor, Wang discloses wherein the etching of the film comprises etching the film by using a wet etching process (the oxidized semiconductor layers, which include SiGeOx, are removed by a wet etching using an etchant such as NH4OH or diluted HF in [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Wang’s method of wherein the etching of the film comprises etching the film by using a wet etching process to the combination of Kwon, Chang and Chen to obtain wherein the etching of the silicon oxide film comprises etching the silicon oxide film by using a wet etching process to removes portions of semiconductor layers ([0032], Wang).
Allowable Subject Matter
Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be
allowable if rewritten in independent form including all of the limitations of the base claim 1 and any intervening claims.
Re: claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner's knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: recited features of the method of claim 6, “…the silicon nitride film is hardly etched based on an etching selectivity of each of the silicon nitride film and the silicon oxide film, and both end portions of the un-etched silicon nitride film protrude with respect to the sidewall of each of the silicon layers…” as recited in claim 12, in combination with remaining features of base claim 1.
Re: claim 13, this inherits the allowable subject matter from claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kao (US 20230060825 A1) teaches “SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF”. This document is related to a manufacturing of semiconductor device including a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
Lung (US 12477775 B2) teaches “NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING”. This document is related to a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898