DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group II, and embodiment in Fig. 4E, in the reply filed on 6/23/2026 is acknowledged.
Claims 1-7, 15-20 have been canceled. Claims 21-33 are added.
Claim 30 recites “a quantity of the one or more first support structures and a quantity of the one or more second support structures are different quantities of support structures”. This feature is not disclosed in the elected embodiment. Thus, this is withdrawn from consideration. Moreover, this is also not disclosed in any of the embodiments in the instant application so this might be supported by the specification of the instant application.
Claim 32 recites “wherein each first support structure of the one or more first support structures is offset from a respective second support structure of the one or more second support structures along the second direction”, which is drawn to the non-elected embodiment in Figs. 9A-9D. Thus, claim 32 is withdrawn from consideration.
Claim 33 recites “wherein an arrangement of the one or more first support structures and an arrangement of the one or more second support structures are mirrored about at least one of the first direction or the second direction” which is drawn to the non-elected embodiment in Figs. 8A-8D. Thus claim 33 is withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-29, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 8643069 B2) in view of Oh et al. (US 2017/0287909 A1).
Regarding claim 21, Hsu teaches a method (Figs. 3-9 of Hsu), comprising:
forming a plurality of active regions (202a, as labeled in Fig. 9) in a substrate (200) of a semiconductor device (device in Fig. 9), wherein the plurality of active regions extend in a first direction (left-to-right direction in Figs. 3-8, which is up-down direction in Fig. 9 of Hsu) in a top-down view of the semiconductor device;
forming a shallow trench isolation (STI) region (202) on the substrate between the plurality of active regions and adjacent to ends of the plurality of fin structures (as shown in Fig. 8);
forming an active gate structure (middle gate 254 in Fig. 8 of Hsu) wherein the active gate structure extends in a second direction (in-out direction of Fig. 3 of Hsu, which is left-right direction in Fig. 9), in the top-down view of the semiconductor device, that is approximately perpendicular with the first direction; and
forming a non-active gate structure (left dummy gate 214 in Fig. 8 of Hsu) that extends in the second direction and is located on the STI region adjacent to ends of the plurality of active regions, wherein the non-active gate structure comprises:
a main body (vertical portion of the gate electrode 254 of gate structure 214) that extends in the second direction; and
one or more support structures (horizontal portion of gate electrode 254) that extend from the main body in the first direction.
But Hsu does not teach that the active regions are fin structures, wherein the plurality of fin structures extend above the STI region, and the active gate structure wraps around the plurality of fin structures on at least three sides of the plurality of fin structures.
Oh teaches a layout method of forming a semiconductor device (Figs. 18A-18B of Oh). The device comprises: a plurality of fin structures (110c-110d in Figs. 18A-18B) extending above an STI region (121 & 135); and active gate structures (165c-165d) wrap around the plurality of fin structures on at least three sides of the plurality of fin structures (as shown in Figs. 18A-18B of Oh).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the active regions as fin structures in order to have increased the device density.
As incorporated, each active region 202a in Fig. 9 of Hsu is analogous to an active region 115c/115d in Fig. 18A-B of Oh. On each active region, a plurality of fin structures are formed together with a gate structure across them, as shown in Fig. 18A-B of Oh.
Regarding claim 22, Hsu in view of Oh teaches all limitations of the method of claim 21, and also teaches wherein the ends of the plurality of fin structures are adjacent to a first side (right side of the left gate 214 in Fig. 8 of Hsu) of the main body; and wherein the one or more support structures extend from a second side (left side) of the main body opposing the first side.
Regarding claim 23, Hsu in view of Oh teaches all limitations of the method of claim 21, and also teaches wherein a distance between the one or more support structures and another active structure in the semiconductor device satisfies a distance threshold (the distance between the horizontal portion of dummy gate 214 and the active gate 210); and wherein the distance threshold is at least two times a size of an active gate structure pitch of the semiconductor device (there is only 1 active gate structure, so this limitation is satisfied automatically).
Regarding claim 24, Hsu in view of Oh teaches all limitations of the method of claim 21,and also teaches wherein the plurality of fin structures comprise a first plurality of fin structures that are included in a first fin group (as combined in claim 21 above, there is a plurality of fin structures in the first active region 202a in Fig. 9 of Hsu);
wherein the active gate structure comprises a first active gate structure (the gate 210/250 in Fig. 8-9 of Hsu across the first fin group) that extends across the first fin group;
wherein the non-active gate structure comprises a first non-active gate structure (the gate 214 in Fig. 8 of Hsu is at the lower side of the active region 202a in Fig. 9 of Hsu) that extends alongside the first active gate structure; and
wherein the method further comprises:
forming a second plurality of fin structures (the fin group on another active region 202a neighboring with lower side of the first active region 202a in Fig. 9 of Hsu), included in a second fin group (the fin group in the second active region) adjacent to the first fin group, that extends in the first direction;
forming a second active gate structure (the active gate 210/250 over the second fin group) that extends across the second fin group in the second direction and wraps around at least three sides of the second plurality of fin structures; and
forming a second non-active gate structure (the dummy gate 214 on the lower side of the second active region 202a of Hsu; the structure of this gate 214 is the same as the first non-active gate structure) adjacent to ends of the second plurality of fin structures and extending alongside the second active gate structure, wherein the second non-active gate structure comprises: a main body (vertical portion of the gate electrode 254 of gate structure 214) that extends in the second direction; and one or more support structures (horizontal portion of gate electrode 254) that extend from the main body of the second non-active gate structure in the first direction.
Regarding claim 25, Hsu in view of Oh teaches all limitations of the method of claim 21, but does not explicitly teach wherein a width of a support structure, of the one or more support structures, in the second direction is included in a range of approximately 1.5 times to approximately 2.5 times a length of the main body in the first direction.
In a different embodiment (Fig. 10), Hsu teaches that the auxiliary dummy structure 212a can be multiple bar-like structure with width W in the range of 0.03 to 0.1 µm and spacing D2 in the range of 0.12 to 0.23 µm (column 8 lines 7 to 24 of Hsu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the auxiliary dummy structure to have multiple bar-like structure, as disclosed by Fig. 10 of Hsu, in order to have improved buffer function (see column 8 lines 30-34 of Hsu).
As incorporated, the width of the support structure of the non-active gate structure of Hsu would be at most the spacing D2 between the bars. So the width of the support structure is about 1.2 times to 7 times the width of the main body of the non-active gate. This range overlaps the claimed range of 1.5 to 2.5 times, thus, a prima facie case of obviousness exists.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the width of a support structure, of the one or more support structures, in the second direction is included in a range of approximately 1.5 times to approximately 2.5 times a length of the main body in the first direction. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 26, Hsu in view of Oh teaches all limitations of the method of claim 21, and also teaches wherein the plurality of fin structures comprise a first plurality of fin structures that are included in a first fin group (as combined in claim 21 above, there is a plurality of fin structures in the first active region 202a in Fig. 9 of Hsu);
wherein the active gate structure comprises a first active gate structure (the gate 210/250 in Fig. 8-9 of Hsu across the first fin group) that extends across the first fin group; and
wherein the method further comprises:
forming a second plurality of fin structures (the group of fins on the active region 202a on the right of the first active region 202a, as shown in Fig. 9 of Hsu), included in a second fin group adjacent to the first fin group, that extends in the first direction; and
forming a second active gate structure (the gate crossing over the second fin group defined above) that extends across the second fin group in the second direction, wherein the non-active gate structure (the non-active gate structure 214 at the upper side of active region 202a as shown in Fig. 9 of Hsu which is the gate 214 to the right of Fig. 8 of Hsu) continuously extends alongside the first active gate structure and the second active gate structure and spans the first fin group and the second fin group (as shown in Fig. 9 of Hsu).
Regarding claim 27, Hsu in view of Oh teaches all limitations of the method of claim 21, but does not explicitly teach wherein a length of a support structure, of the one or more support structures, in the first direction is included in a range of approximately 1.5 times to approximately 2.5 times a length of the main body in the first direction.
In a different embodiment (Fig. 10), Hsu teaches that the auxiliary dummy structure 212a can be multiple bar-like structure with width W in the range of 0.03 to 0.1 µm and spacing D2 in the range of 0.12 to 0.23 µm (column 8 lines 7 to 24 of Hsu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the auxiliary dummy structure to have multiple bar-like structure, as disclosed by Fig. 10 of Hsu, in order to have improved buffer function (see column 8 lines 30-34 of Hsu).
As incorporated, the width of the support structure of the non-active gate structure of Hsu would be at most the spacing D2 between the bars. So the width of the support structure is about 1.2 times to 7 times the width of the main body of the non-active gate. This range overlaps the claimed range of 1.5 to 2.5 times, thus, a prima facie case of obviousness exists.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the width of a support structure, of the one or more support structures, in the second direction is included in a range of approximately 1.5 times to approximately 2.5 times a length of the main body in the first direction. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 28, Hsu teaches a method (Figs. 3-9 of Hsu), comprising:
forming one or more first active regions (202a, as labeled in Fig. 9) extending above a substrate (200) of a semiconductor device (device in Fig. 3-9 of Hsu), wherein the one or more first active regions extend in a first direction (left-to-right direction in Figs. 3-8, which is up-down direction in Fig. 9 of Hsu) in a top-down view (view in Fig. 9 of Hsu) of the semiconductor device;
forming a first active gate structure (middle gate 210/250 in Fig. 8 of Hsu), wherein the first active gate structure extends in a second direction (in-out direction of Fig. 3 of Hsu, which is left-right direction in Fig. 9), in the top-down view of the semiconductor device, that is approximately perpendicular with the first direction (as shown in Fig. 9 of Hsu); and
forming a first non-active gate structure (left dummy gate 214 in Fig. 8 of Hsu) on a shallow trench isolation (STI) region (202), wherein the first non-active gate structure is adjacent to ends of the one or more first active regions (as shown in Fig. 8), and wherein the first non-active gate structure comprises: a first main body (vertical portion of the structure 214) that extends in the second direction; and one or more first support structures (horizontal portion of the structure 214) that extend from the first main body in the first direction;
forming one or more second active region (the active region 202a next to the first active region in Fig. 9) extending above the substrate, wherein the one or more second active regions extend in the first direction;
forming a second active gate structure (250 of the second active region), wherein the second active gate structure extends in the second direction (as shown in Fig. 9 of Hsu); and
forming a second non-active gate structure (left dummy gate 214 in Fig. 8 of Hsu over the second active region) on the STI region and adjacent to the first non-active gate structure, wherein the second non-active gate structure is adjacent to ends of the one or more second active regions (lower end of the second active region 202a), and wherein the second non-active gate structure comprises: a second main body (vertical portion of the second dummy gate structure 214) that extends in the second direction; and one or more second support structures (horizontal portion of the structure 214) that extend from the second main body in the first direction.
But Hsu does not teach that the one or more first active regions are first fin structures; the first active gate structure wraps around the one or more first active regions on at least three sides of the one or more first fin structures; the one or more second active regions are second fin structures; the second active gate structure wraps around the one or more second fin structures on at least three sides of the one or more second fin structures.
Oh teaches a layout method of forming a semiconductor device (Figs. 18A-18B of Oh). The device comprises: a plurality of fin structures (110c-110d in Figs. 18A-18B) extending above an STI region (121 & 135); and active gate structures (165c-165d) wrap around the plurality of fin structures on at least three sides of the plurality of fin structures (as shown in Figs. 18A-18B of Oh).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the active regions as fin structures in order to have increased the device density.
As incorporated, each active region 202a in Fig. 9 of Hsu is analogous to an active region 115c/115d in Fig. 18A-B of Oh. On each active region, a plurality of fin structures are formed together with a gate structure across them, as shown in Fig. 18A-B of Oh.
Regarding claim 29, Hsu in view of Oh teaches all limitations of the method of claim 28, and also teaches wherein a quantity of the one or more first support structures and a quantity of the one or more second support structures are a same quantity of support structures (as suggested in Figs. 8-9 of Hsu, each of the ).
Regarding claim 31, Hsu in view of Oh teaches all limitations of the method of claim 28, and also teaches wherein each first support structure of the one or more first support structures is aligned with a respective second support structure of the one or more second support structures along the second direction (as the gate lines are aligned, the horizontal portions are also aligned).
Allowable Subject Matter
Claims 8-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, the prior art of record does not disclose or fairly suggests a method, comprising: “etching the one or more dummy gate layers based on a pattern to form: one or more first dummy gate structures that extend in a second direction, in the top-down view of the semiconductor device, that is approximately perpendicular with the first direction, wherein the one or more first dummy gate structures wrap around the plurality of fin structures on at least three sides of the plurality of fin structures; and one or more second dummy gate structures that extend in the second direction and are located on the STI region adjacent to ends of the plurality of fin structures, wherein the one or more second dummy gate structures comprise: a main body that extends in the second direction; and one or more support structures that extend from the main body in the first direction” along with other limitations of the claim.
The prior art of record are Oh et al. (US 2017/0287909 A1) and Ning et al. (US 2015/0287651 A1).
Oh teaches a method, comprising: forming a plurality of fin structures (110 in Fig. 31B of Oh) in a substrate (105) of a semiconductor device (device in Fig. 35B), wherein the plurality of fin structures extend in a first direction (x-direction in Fig. 30) in a top-down view of the semiconductor device; forming a shallow trench isolation (STI) region (121 and 135 in Fig. 34A-34B of Oh) on the substrate between the plurality of fin structures and adjacent to ends of the plurality of fin structures (as shown in Fig. 34A-B); forming one or more dummy gate layers (as stated in [0101], the gate lines 165c-165d of Figs. 35A-35Bare formed by patterning. So a blanket dummy gate layer being formed before the etching/patterning of the gate lines is implicit) on the STI region and around the plurality of fin structures (as shown in Figs. 35A-35B); etching the one or more dummy gate layers (the patterning to form the gate lines as described in [0101]) based on a pattern to form: one or more first dummy gate structures (165c-165d over the fins 110c-110d in Fig. 35A) that extend in a second direction (y-direction in Fig. 30), in the top-down view of the semiconductor device, that is approximately perpendicular with the first direction; and one or more second dummy gate structures (the auxiliary gate structures 165 over the STI region 135 in Fig. 35A of Oh) that extend in the second direction and are located on the STI region adjacent to ends of the plurality of active regions.
Ning teaches a layout and structure of overlay mark on the substrate (101 and 105 in Figs. 1A-1B or 201 and 205 in Figs. 2A-2B of Ning). The overlay marks have comb-shape or cross shape including main body and fingers. However, there is no indication that these overlay marks are formed in the same layer as the dummy gate layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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