DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 2. The information disclosure statement (IDS) submitted on June 1, 2023, has been fully considered by the examiner. Specification 3. The abstract of the disclosure is objected to because of the following informalities. Line 3 recites, “ The plurality of cells in each cell strings include …,” which Examiner believes should read, “ The plurality of cells in each cell strings include string include s … ”. Line 5 recites, “… that may occur due toa change …,” which Examiner believes should read, “… that may occur due [[toa]] to a change …”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 112 4. The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. 5. Claim s 11 and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 6 . Claim 17 recites the limitation “ the vertical NAND flash type semiconductor device ” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “ the vertical NAND flash type semiconductor device ” shall be interpreted as “the semiconductor device including vertical NAND flash,” which finds antecedent basis in claim 12. 7. Claims 11 and 18 recite the limitation, “ a sum of the resistances of the plurality of cells of the cell string when a pass voltage is applied to gates of each of the plurality of cells of the cell string is substantially equal to a predetermined constant. ” The meaning of this limitation is indefinite. This limitation appears to reference ¶ [0058], which states in part, “ a sum of the compensation substring resistance and an effective substring resistance of the effective cells SC10 is substantially equal to a constant K. ” However, no definition is given for “K,” nor is any range defined or importance ascribed. Within this context, any sum could be said to be “substantially equal to a constant K” or “substantially equal to a predetermined constant.” Therefore, the meaning of the limitation is indefinite. Claim Rejections - 35 USC § 103 8 . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 9 . The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10 . The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . 1 1 . Claims 1- 6, 8, and 12-1 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al ( US 20180143762 A1 ), hereinafter Kim, in view of Chin, et al ( US 20080273388 A1 ), hereinafter Chin . Regarding independent claim 1, Kim teaches a vertical NAND flash type semiconductor device ( FIG. 5 ; ¶ [00 76 ] ) comprising: a plurality of cell strings extending vertically ( FIG. 5 , NAND strings coupled to BL1..BL4 ) , each comprising a plurality of cells connected in series vertically ( FIG. 5 , e.g., data memory cells MC are shown connected in series ) , the plurality of cells in each of the plurality of cell strings including a plurality of effective cells ( FIG. 5 , data memory cells MC connected to WL 1..WL8 ; ¶ [00 71 ] ) and a plurality of compensation cells ( FIG. 5 , dummy memory cells connected to D MC1 , D MC2 ; ¶ [00 71-0072 ] ) . Kim does not teach the vertical NAND flash type semiconductor device is configured to control a change in a string resistance of a cell string by controlling resistance states of the plurality of compensation cells according to resistance states of the plurality of effective cells in each of the plurality of cell strings. Chin teaches a NAND flash type semiconductor device ( FIG. 4; ¶ [0012] ) is configured to control a change in a string resistance of a cell string by controlling resistance states of the plurality of compensation cells ( FIG. 4, coupled to WL_d0 and WL_d1; ¶ [0012], [0047] ) according to resistance states of the plurality of effective cells in each of the plurality of cell strings ( ¶ [0012] teaches “By selectively programming memory cells on the dummy word lines, the resistances of the NAND strings (or other groups of memory cells) can be changed to account for shifts in resistance due to programming of data into the NAND strings (or other groups of memory cells)” ) . Regarding independent claim 1 2 , Kim teaches a method ( e.g., FIG. 3 ) of operating a semiconductor device including vertical NAND flash ( FIG. 5; ¶ [00 76 ] ) , the method comprising: partitioning each of a plurality of cells in a plurality of cell strings ( FIG. 5 , NAND strings coupled to BL1..BL4 ) of the vertical NAND flash into a plurality of effective cells ( FIG. 5 , data memory cells MC connected to WL 1..WL8; ¶ [00 71 ] ) and a plurality of compensation cells ( FIG. 5 , dummy memory cells connected to D MC1 , D MC2; ¶ [00 71-0072 ] ) . Kim does not teach controlling a change in string resistance of a cell string of the plurality of cell strings by controlling resistance states of the plurality of compensation cells of the cell string according to resistance states of the plurality of effective cells of the cell string. Chin teaches controlling a change in string resistance of a cell string of the plurality of cell strings by controlling resistance states of the plurality of compensation cells ( FIG. 4, coupled to WL_d0 and WL_d1; ¶ [0012], [0047] ) of the cell string according to resistance states of the plurality of effective cells of the cell string ( ¶ [0012] teaches “By selectively programming memory cells on the dummy word lines, the resistances of the NAND strings (or other groups of memory cells) can be changed to account for shifts in resistance due to programming of data into the NAND strings (or other groups of memory cells)” ). Regarding independent claim s 1 and 1 2 , i t would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Chin into the method of Kim to include selectively programming memory cells on the dummy word lines . The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of changing the resistances of the NAND strings (or other groups of memory cells) to account for shifts in resistance due to programming of data into the NAND strings (or other groups of memory cells) ( Chin, ¶ [0012] ) . Regarding claim 2, Kim as modified by Chin teaches the limitations of claim 1. Chin further teaches each of the plurality of cells has a plurality of resistance states ( e.g., referencing FIG. 13, ¶ [0094] teaches concerning data memory cells (“effective cells”), “In step 902, the system determines the number of high data states in the second group of memory cells. Assume that states 12-15 are high data states. Thus, the system will count the number of memory cells in the second group that have data stored in data states 12-15. The high data states are associated with higher threshold voltages, which have a greater impact on resistance.” Note also FIG. 13 refers to “high data states” as “high R states.” Concerning dummy memory cells (“compensation cells”), ¶ [0094] teaches, “set the threshold voltage of the dummy memory cell to data state zero, data state 7 or data state 15. As described above, greater resolution can be achieved by using all the data states or an analog value.” ¶ [0086] explain s , “the memory cells can be programmed into any of the data states, thereby, providing more resolution in how the resistance of the NAND string is tuned.” ) , and the plurality of resistance states include a first resistance state and a second resistance state corresponding to an inverse resistance state of the first resistance state ( ¶ [0054] of the present application teaches, “the first resistance state may be referred to as an erased state, and the second resistance state may be referred to as a programmed state. The second resistance state may be referred to as an inverse resistance state of the first resistance state. The first resistance state may correspond to data '1' and the second resistance state may correspond to data '0', or vice versa.” C hin Claim 2 teaches, “ threshold voltage data that can be used to determine information about resistance, or stored data that can be used to determine information about resistance; and said information indicative of a resistance characteristic can pertain to all of said data non-volatile storage elements or a subset of said data non-volatile storage elements. ” That is, the programmed threshold voltage and corresponding data may be associated with resistance states; therefore resistances of an erased state and its “inverse” (programmed) state may be “first” and “second” resistance states. ) , and wherein the vertical NAND flash type semiconductor device is configured to adjust a number of effective cells having the first resistance state among the plurality of effective cells and a number of compensation cells having the second resistance state among the plurality of compensation cells to a predetermined ratio in each of the plurality of cell strings ( The present application indicates in ¶ [0053] “ The predetermined ratio may be, for example, 1:1. However, in some cases, the predetermined ratio may be 1:2, 1:3, 1:4, or the like.” Chin ¶ [0090], for example, teaches “FIG. 12B describes an embodiment that uses only one of the dummy memory cells per NAND string…In some embodiments, there could be many dummy word lines, however, only a subset of dummy word lines are used to effect resistance.” That is, Chin accommodates a widely-varying number of “predetermined ratios.” For example, i n Chin’s embodiment using one dummy cell per NAND string, when the number of the data memory cells is “adjusted” so all are at a “first resistance state,” the predetermined ratio will be [ one compensation cell ] : [ the number of effective cells ] . ) . Regarding claim 3 , Kim as modified by Chin teaches the limitations of claim 2. Kim does not teach the range of the predetermined ratio is 1:1 as cited in the claimed limitation . However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A). Regarding claim 4 , Kim as modified by Chin teaches the limitations of claim 1. Kim does not teach the range of a number of the plurality of compensation cells in each of the plurality of cell strings is one-third or more of a number of the plurality of effective cells in each of the plurality of cell strings. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A). Regarding claim 5 , Kim as modified by Chin teaches the limitations of claim 1. Kim does not teach the range of a number of the plurality of compensation cells in each of the plurality of cell strings is equal to a number of the plurality of effective cells in each of the plurality of cell strings ( i.e., a 1:1 ratio of compensation cells to effective cells ) . However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A). Regarding claim 6, Kim as modified by Chin teaches the limitations of claim 1. Chin further teaches each of the plurality of cells is a binary cell ( ¶ [0037] teaches “When storing one bit of digital data (referred to as a binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data ‘1’ and ‘0’” ) having a first resistance state and a second resistance state ( e.g., ¶ [0065-0066] teach “dummy memory cells can have their threshold voltage set to any of a number of analog levels” and “Increasing the threshold voltage of the dummy memory cell increases the resistance of the NAND string. Decreasing the threshold voltage of the dummy memory cell decreases the resistance of the NAND string.” Claim 2 teaches, “threshold voltage data that can be used to determine information about resistance, or stored data that can be used to determine information about resistance .” ) . Regarding claim 8 , Kim as modified by Chin teaches the limitations of claim 1. Chin further teaches each of the plurality of cells has a multi-level cell (¶ [0038] teaches “A memory cell can also store multiple levels of information (referred to as a multi-state memory cell) ) having three or more resistance states ( e.g., ¶ [0065-0066] teach “dummy memory cells can have their threshold voltage set to any of a number of analog levels” and “Increasing the threshold voltage of the dummy memory cell increases the resistance of the NAND string. Decreasing the threshold voltage of the dummy memory cell decreases the resistance of the NAND string. ” Claim 2 teaches, “ threshold voltage data that can be used to determine information about resistance, or stored data that can be used to determine information about resistance . ” ¶ [0094] teaches, “set the threshold voltage of the dummy memory cell to data state zero, data state 7 or data state 15. ” ) . Regarding claim 13, Kim as modified by Chin teaches the limitations of claim 12. Chin further teaches each of the plurality of cells has a plurality of resistance states ( e.g., referencing FIG. 13, ¶ [0094] teaches concerning data memory cells (“effective cells”), “In step 902, the system determines the number of high data states in the second group of memory cells. Assume that states 12-15 are high data states. Thus, the system will count the number of memory cells in the second group that have data stored in data states 12-15. The high data states are associated with higher threshold voltages, which have a greater impact on resistance.” Note also FIG. 13 refers to “high data states” as “high R states.” Concerning dummy memory cells (“compensation cells”), ¶ [0094] teaches, “set the threshold voltage of the dummy memory cell to data state zero, data state 7 or data state 15. As described above, greater resolution can be achieved by using all the data states or an analog value.” ¶ [0086] explain s , “the memory cells can be programmed into any of the data states, thereby, providing more resolution in how the resistance of the NAND string is tuned.” ) , and the plurality of resistance states include a first resistance state and a second resistance state corresponding to an inverse resistance state of the first resistance state ( ¶ [0054] of the present application teaches, “the first resistance state may be referred to as an erased state, and the second resistance state may be referred to as a programmed state. The second resistance state may be referred to as an inverse resistance state of the first resistance state. The first resistance state may correspond to data '1' and the second resistance state may correspond to data '0', or vice versa.” Chin Claim 2 teaches, “ threshold voltage data that can be used to determine information about resistance, or stored data that can be used to determine information about resistance; and said information indicative of a resistance characteristic can pertain to all of said data non-volatile storage elements or a subset of said data non-volatile storage elements. ” That is, the programmed threshold voltage and corresponding data may be associated with resistance states; therefore resistances of an erased state and its “inverse” (programmed) state may be “first” and “second” resistance states. ) , and wherein controlling the change in string resistance of the cell string comprises adjusting a number of effective cells having the first resistance state among the plurality of effective cells of the cell string and a number of compensation cells having the second resistance state among the plurality of compensation cells of the cell string to a predetermined ratio ( The present application indicates in ¶ [0053] “The predetermined ratio may be, for example, 1:1. However, in some cases, the predetermined ratio may be 1:2, 1:3, 1:4, or the like.” Chin ¶ [0090], for example, teaches “FIG. 12B describes an embodiment that uses only one of the dummy memory cells per NAND string…In some embodiments, there could be many dummy word lines, however, only a subset of dummy word lines are used to effect resistance.” That is, Chin accommodates a widely-varying number of “predetermined ratios.” For example, i n Chin’s embodiment using one dummy cell per NAND string, when the number of the data memory cells is “adjusted” so all are at a “first resistance state,” the predetermined ratio will be [one compensation cell]:[the number of effective cells]. ). Regarding claim 14 , Kim as modified by Chin teaches the limitations of claim 13. Kim does not teach the range of the predetermined ratio is 1:1 as cited in the claimed limitation. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A). Regarding claim 15, Kim as modified by Chin teaches the limitations of claim 12. Kim does not teach the range of a number of the plurality of compensation cells in each of the plurality of cell strings is equal to a number of the plurality of effective cells in each of the plurality of cell strings. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A). 1 2 . Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al ( US 20180143762 A1 ), hereinafter Kim, in view of Chin, et al ( US 20080273388 A1 ), hereinafter Chin, and further in view of Tran, et al ( US 20220374161 A1 ), hereinafter Tran. Regarding claim 9, Kim as modified by Chin teaches the limitations of claim 1. Kim further teaches a plurality of bit lines respectively connected to the plurality of cell strings are provided ( FIG. 5, BL1..BL4 ). Kim does not teach the vertical NAND flash type semiconductor device is configured to sum current values measured in at least two bit lines among the plurality of bit lines. Tran teaches the vertical NAND flash type semiconductor device is configured to sum current values measured in at least two bit lines among the plurality of bit lines ( FIG. 30 and ¶ [0071] teach outputs are generated on bit lines (see also ¶ [0029]); referencing FIG. 7, ¶ [0030] teaches “The output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution” (see also FIG. 31) ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Tran into the method of Kim to include summing output bit line currents of the memory cell array. The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of creating a single value for the convolution operation for use by the next layer (Tran ¶ [0029-0032]). 1 3 . Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al ( US 20180143762 A1 ), hereinafter Kim, in view of Chin, et al ( US 20080273388 A1 ), hereinafter Chin, and further in view of Zhang ( US 20220398439 A1 ). Regarding claim 10, Kim as modified by Chin teaches the limitations of claim 1. Kim further teaches the plurality of effective cells are synaptic cells mimicking a synapse ( S ee neural network of FIG. 21; ¶ [0177-0180] . While Kim does not use the term “synapse,” comparing Kim FIG. 21 and ¶ [0177-0180] to the artificial neuron/synapse of Zhang FIG. 9 and ¶ [0101] makes it clear an artificial neuron/synapse is in view in Kim ), and the vertical NAND flash type semiconductor device is a neuromorphic device (¶ [0189]; FIG. 24 shows the neuromorphic processor as separate from the memory array, which appears consistent with FIG. 9 of the present application, in which the memory array is distinct from the “neuron circuit” ) . Regarding claim 17, Kim as modified by Chin teaches the limitations of claim 12. Kim further teaches the plurality of effective cells are synaptic cells mimicking a synapse ( S ee neural network of FIG. 21; ¶ [0177-0180] . While Kim does not use the term “synapse,” comparing Kim FIG. 21 and ¶ [0177-0180] to the artificial neuron/synapse of Zhang FIG. 9 and ¶ [0101] makes it clear an artificial neuron/synapse is in view in Kim. ) , and the vertical NAND flash type semiconductor device is a neuromorphic device (¶ [0189]; FIG. 24 shows the neuromorphic processor as separate from the memory array, which appears consistent with FIG. 9 of the present application, in which the memory array is distinct from the “neuron circuit” ) . 1 4 . Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, et al ( US 20180143762 A1 ), hereinafter Kim , in view of Chin, et al ( US 20080273388 A1 ), hereinafter Chin, and further in view of Mokhlesi , et al ( US 20080158967 A1 ), hereinafter Mokhlesi . Regarding claim 11, Kim as modified by Chin teaches the limitations of claim 1. Chin further teaches controlling the change in the string resistance of the cell string comprises controlling respective values of the plurality of compensation cells in the cell string so that a sum of the resistances of the plurality of cells of the cell string is substantially equal to a predetermined constant ( FIG. 11, 804, 812, 814; ¶ [0083] teaches adjusting dummy cells to compensate for the difference in “resistance characteristic” between an even distribution (“predetermined constant”) and actual data. The resistance characteristic may be the actual resistance of the memory cell s (i.e., sum of cell resistances in a string) , or an average of data state values (sum divided by number of cells). ¶ [0085] teaches the goal of the compensation is to “move toward a resistance for a NAND string with an even distribution” – i.e., to be “substantially equal” to the “predetermined constant” of an even distribution. ) . Kim does not teach the sum of resistances is substantially equal to a predetermined constant when a pass voltage is applied to gates of each of the plurality of cells of the cell string . Mokhlesi teaches in FIG. 14 and ¶ [0100] using a “high enough voltage so that the memory cells with the highest threshold turn on” (i.e., a pass voltage) to determine “whether the NAND string is in a high resistance state or low resistance state . ” Therefore, Kim as modified by Chin and Mokhlesi teaches controlling the change in the string resistance of the cell string comprises controlling respective values of the plurality of compensation cells in the cell string so that a sum of the resistances of the plurality of cells of the cell string when a pass voltage is applied to gates of each of the plurality of cells of the cell string is substantially equal to a predetermined constant. Regarding claim 18, Kim as modified by Chin teaches the limitations of claim 12. Chin further teaches controlling the change in the string resistance of the cell string comprises controlling respective values of the plurality of compensation cells in the cell string so that a sum of the resistances of the plurality of cells of the cell string is substantially equal to a predetermined constant ( FIG. 11, 804, 812, 814; ¶ [0083] teaches adjusting dummy cells to compensate for the difference in “resistance characteristic” between an even distribution (“predetermined constant”) and actual data. The resistance characteristic may be the actual resistance of the memory cells (i.e., sum of cell resistances in a string) , or an average of data state values (sum divided by number of cells). ¶ [0085] teaches the goal of the compensation is to “move toward a resistance for a NAND string with an even distribution” – i.e., to be “substantially equal” to the “predetermined constant” of an even distribution. ) . Kim does not teach the sum of resistances is substantially equal to a predetermined constant when a pass voltage is applied to gates of each of the plurality of cells of the cell string . Mokhlesi teaches in FIG. 14 and ¶ [0100] using a “high enough voltage so that the memory cells with the highest threshold turn on” (i.e., a pass voltage) to determine “whether the NAND string is in a high resistance state or low resistance state . ” Therefore, Kim as modified by Chin and Mokhlesi teaches controlling the change in the string resistance of the cell string comprises controlling respective values of the plurality of compensation cells in the cell string so that a sum of the resistances of the plurality of cells of the cell string when a pass voltage is applied to gates of each of the plurality of cells of the cell string is substantially equal to a predetermined constant. Regarding claims 11 and 18, It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Mokhlesi into the method of Kim to include pass voltages calibrated to a sense amplifier trip point. The ordinary artisan would have been motivated to modify Kim in the above manner for the purpose of distinguishing high and low resistance NAND strings ( Mokhlesi ¶ [0100]). Allowable Subject Matter 15. Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 16. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 7 , the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the vertical NAND flash type semiconductor device is configured to equalize a number of effective cells having the first resistance state among the plurality of effective cells and a number of compensation cells having the second resistance state among the plurality of compensation cells in each of the plurality of cell strings. Regarding claim 16 , the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of controlling the change in string resistance of the cell string comprises equalizing a number of effective cells having the first resistance state among the plurality of effective cells of the cell string and a number of compensation cells having the second resistance state among the plurality of compensation cells of the cell strings. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRADLEY COON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0740 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8am-5pm (Eastern) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT AMIR ZARABIAN can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1852 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.S.C./ Examiner, Art Unit 2827 /AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827