DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on July 2, 2026.
Claims 1, 11-12, and 17-18 are amended. Claims 6-7 are canceled. Claim 19 is added.
Applicant’s amendments to the specification submitted on July 2, 2026 are acknowledged and objections to the specification are withdrawn.
Applicant’s amendments to claims 11 and 17-18 overcome the 112(b) rejection set forth in the previous office action and therefore the 112(b) rejection is withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 8-11, filed July 2, 2026, with respect to independent claims 1 and 12, have been fully considered and are persuasive. The rejections under 35 USC § 103 have been withdrawn.
Applicant asserts neither Kim nor Chin teaches controlling at least one compensation cell to have a second resistance state, corresponding to an inverse resistance state of a first resistance state, according to at least one effective cell having the first resistance state, as recited in amended claim 1.
¶[0054] of the present application teaches, “the first resistance state may be referred to as an erased state, and the second resistance state may be referred to as a programmed state. The second resistance state may be referred to as an inverse resistance state of the first resistance state. The first resistance state may correspond to data '1' and the second resistance state may correspond to data '0', or vice versa.” That is, it appears in the present application an erased state is the “inverse state” of a programmed state and vise-versa.
Chin ¶[0094] teaches, “set the threshold voltage of the dummy memory cell to data state zero, data state 7 or data state 15. As described above, greater resolution can be achieved by using all the data states or an analog value.” Chin ¶[0086] explains, “the memory cells can be programmed into any of the data states, thereby, providing more resolution in how the resistance of the NAND string is tuned.” Therefore, Chin teaches a dummy cell (which is being used as a “compensation” cell) may be in an erased (“first resistance state”) or programmed (“second resistance state”) state.
However, Applicant further submits neither Kim nor Chin teaches the recited correspondence in which at least one compensation cell is controlled "to have the second resistance state" (i.e., programmed) according to at least one effective cell "having the first resistance state" (i.e., erased). That is, amended claim 1 as recited mandates if at least one memory cell is erased, at least one compensation cell must be programmed. Chin’s method leaves open the possibility that both dummy/compensation cells may be erased when at least one memory cell is erased. That is, Chin does not take into account the state on an individual cell in the memory string when determining the state of a compensation cell, rather considering an estimate of the overall string resistance.
Therefore, Applicant’s arguments are persuasive in light of the amendments and the rejections of claims 1 and 12 as set forth in the previous office action are withdrawn.
Claim Objections
4. Claim 18 is objected to because of the following informalities: There is a duplicate instance of the word, “constant,” at the end of the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 2-3, 13-14, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 repeats in lines 2-3 limitations of independent claim 1, lines 6-7, which causes the corresponding limitations of claim 2 to be indefinite. To correct, Examiner recommends the following. Claim 3 depends on claim 2.
Claim 2. The vertical NAND flash type semiconductor device of claim 1, wherein the vertical NAND flash type semiconductor device is configured to adjust a number of effective cells having the first resistance state among the plurality of effective cells and a number of compensation cells having the second resistance state among the plurality of compensation cells to a predetermined ratio in each of the plurality of cell strings.
Claim 13 repeats in lines 2-4 limitations of independent claim 12, lines 5-6, which causes the corresponding limitations of claim 13 to be indefinite. To correct, Examiner recommends the following. Claim 14 depends on claim 13.
Claim 13. The method of claim 12, wherein the second resistance state corresponds to an inverse resistance state of the first resistance state, and wherein controlling the change in string resistance of the cell string comprises adjusting a number of effective cells having the first resistance state among the plurality of effective cells of the cell string and a number of compensation cells having the second resistance state among the plurality of compensation cells of the cell string to a predetermined ratio.
Claim 16 repeats in lines 1-2 limitations of independent claim 12, lines 5-6, which causes the corresponding limitations of claim 16 to be indefinite. To correct, Examiner recommends the following.
Claim 16. The method of claim 15, wherein controlling the change in string resistance of the cell string comprises equalizing a number of effective cells having the first resistance state among the plurality of effective cells of the cell string and a number of compensation cells having the second resistance state among the plurality of compensation cells of the cell strings.
Allowable Subject Matter
7. Claims 1, 4-5, 8-12, 15, 17, and 19 are allowed.
Claims 2-3, 13-14, and 16 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 18 would be allowable if rewritten to overcome the objection set forth in this Office action.
8. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the vertical NAND flash type semiconductor device is configured to control a change in a string resistance of a cell string by controlling at least one compensation cell of the plurality of compensation cells to have the second resistance state according to at least one effective cell of the plurality of effective cells having the first resistance state in each of the plurality of cell strings. Claims 2-5 and 8-11 depend on Claim 1.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of controlling a change in string resistance of a cell string of the plurality of cell strings by controlling at least one compensation cell of the plurality of compensation cells to have the second resistance state according to at least one effective cell of the plurality of effective cells having the first resistance state in each of the plurality of cell strings. Claims 13-18 depend on Claim 12.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a number of the plurality of compensation cells in each of the plurality of cell strings is equal to a number of the plurality of effective cells, and wherein the vertical NAND flash type semiconductor device is configured to equalize a number of effective cells having the first resistance state among the plurality of effective cells and a number of compensation cells having the second resistance state among the plurality of compensation cells in each of the plurality of cell strings.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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