Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1).
Regarding independent claim 1: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 19-30 for the manufacturing steps for making device of Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a method, comprising:
forming a semiconductor device ([0155]-[0156]: TR1 with active regions A11, A12 or TR2 with active regions A21, A22) over a front-side of a substrate ([0155]-[0156]: 100), the semiconductor device comprising:
a channel region ([0157]-[0160]: region between source/drain regions 160),
a gate structure ([0157]: G1) across the channel region, and
source/drain regions ([0157]-[0158]: 160) on the channel region and at opposite sides of the gate structure (G1);
forming a first source/drain contact ([0159]-[0160]: CA1) on a first one of the source/drain regions;
forming a front-side interconnect structure ([0163]: FV1/FM1) over the first source/drain contact;
forming a first dielectric through-silicon via ([0169]-[0171]: TV1) extending through the substrate from a cross-sectional view (FIG. 28),
the first dielectric through-silicon via (TV1) overlapping the first source/drain contact (CA1) from a top view (FIG. 28; [0160]); and
forming a back-side interconnect structure ([0173]: BM1) over a back-side of the substrate (100),
wherein the first dielectric through-silicon via (TV1) has a back-side surface in contact with the back-side interconnect structure (BM1).
Although, Oh does not expressly teach
etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via.
Nishio teaches (e.g., Figs. 1A-4C) a method, comprising forming a substrate ([0054]: 1);
Nishio further teaches etching the substrate ([0060]: 1) to form a through-silicon via opening ([0060]: 14);
filling an entirety of the through-silicon via opening with a dielectric material ([0061]: 15) to form a first dielectric through-silicon via ([0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via, as taught by Nisio, for the benefits of reducing or eliminating interconnect material that can cause defects, when forming internal interconnects of the semiconductor device above the through holes 14 in a later step (Nishio: [0062]).
Alternatively, should the limitation “filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via” to be interpreted as the through-silicon via comprised only of dielectric in its final step, then this limitation is taught below:
Claims 1, 2, 7-8, 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1).
Regarding independent claim 1: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 19-30 for the manufacturing steps for making device of Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a method, comprising:
forming a semiconductor device ([0155]-[0156]: TR1 with active regions A11, A12 or TR2 with active regions A21, A22) over a front-side of a substrate ([0155]-[0156]: 100), the semiconductor device comprising:
a channel region ([0157]-[0160]: region between source/drain regions 160),
a gate structure ([0157]: G1) across the channel region, and
source/drain regions ([0157]-[0158]: 160) on the channel region and at opposite sides of the gate structure (G1);
forming a first source/drain contact ([0159]-[0160]: CA1) on a first one of the source/drain regions;
forming a front-side interconnect structure ([0163]: FV1/FM1) over the first source/drain contact;
forming a first dielectric through-silicon via ([0169]-[0171]: TV1) extending through the substrate from a cross-sectional view (FIG. 28),
the first dielectric through-silicon via (TV1) overlapping the first source/drain contact (CA1) from a top view (FIG. 28; [0160]); and
forming a back-side interconnect structure ([0173]: BM1) over a back-side of the substrate (100),
wherein the first dielectric through-silicon via (TV1) has a back-side surface in contact with the back-side interconnect structure (BM1).
Oh does not expressly teach
etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via.
Yoshida teaches (e.g., Fig. 4) a method comprising etching a substrate ([0064]-[0065]) to form a through-silicon via opening ([0064]-[0065]), filling an entirety of a through-silicon via opening with a dielectric material to form a first dielectric through-silicon via ([0065]: 176).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via, as taught by Yoshida, for the benefits of completely protecting the integrated circuit device from signal interference of adjacent devices and thus improving device resilience.
Regarding claim 2: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via is made of a material having a thermal conductivity greater than about 150 W/m/K ([0015]-[0018] and [0025]: Figs. 2-5 are cross-sections of Fig. 1; [0111]: silicon oxycarbonitride (SiOCN); as used in the specification [0017] the term “about” is considered within 20%; this meets the claim limitation).
Regarding claim 7: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the back-side interconnect structure comprises a dielectric layer ([0094]: 321) and a metal line laterally (Fig. 7; [0119]-[0120]: metal line BM1 laterally extending between the dielectric layer) extending in the dielectric layer (321), and
the back-side surface of the first dielectric through-silicon via (194) is in contact with the metal line (BM1).
Regarding claim 8: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the back-side interconnect structure ([0173]: BM1) comprises
a dielectric layer ([0094]: 321), a metal line laterally extending (Fig. 7; [0119]-[0120]: metal line BM1 laterally extending between the dielectric layer) in the dielectric layer (321), and
a dielectric lateral structure in the dielectric layer (Fig. 7; [0177]), and
the back-side surface of the first dielectric through-silicon via (194) is in contact with the dielectric lateral structure (321).
Regarding claim 10: Oh teaches the claim, limitation of the method of claim 8, on which this claim depends,
further comprising: forming a buried power rail ([0164]: PW11) on the front-side of the substrate (Fig. 7; [0170]: upper surface of substrate 100); and
forming a metal through-silicon via ([0171]: 192) extending through the substrate,
the metal through-silicon via (192) having a front-side surface in contact with the buried power rail (PW11), and a back-side surface in contact with the metal line (BM1) of the back-side interconnect structure.
Regarding claim 23: Oh teaches the claim, limitation of the semiconductor structure of claim 16, on which this claim depends.
Oh does not expressly teach that the dielectric TSV occupies an entire cross-sectional area of a through-silicon via opening within the first semiconductor substrate.
Yoshida teaches (e.g., Fig. 4) a semiconductor structure comprising a substrate ([0064]-[0065]) and a through-silicon via opening ([0064]-[0065]);
Yoshida further teaches that the dielectric TSV occupies an entire cross-sectional area of a through-silicon via opening within the first semiconductor substrate (Fig. 4; [0065]: 176).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Oh, the dielectric TSV occupying an entire cross-sectional area of the through-silicon via opening within the first semiconductor substrate, as taught by Yoshida, for the benefits of completely protecting the integrated circuit device from signal interference of adjacent devices and thus improving device resilience.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1) as applied above and further in view of Nishio et al. (US 2010/0283130 A1).
Regarding claim 5: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via (194) has a front-side surface in contact with the first source/drain contact (160).
Oh as modified by Yoshida does not teach expressly teach that the first dielectric through-silicon via has a front-side surface in direct contact with the first source/drain contact.
Nishio teaches a first dielectric through-silicon via ([0069]: 12/13) having a front-side surface in direct contact with a first source/drain contact ([0063]: 7/8a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method wherein the first dielectric through-silicon via has a front-side surface in direct contact with the first source/drain contact, as taught by Nishio, for the benefits of reducing signal delays of the device in operation.
Regarding claim 6: Oh teaches the claim, limitation of the method of claim 5, on which this claim depends, further comprising:
forming a second source/drain contact (Fig. 7; [0119]-[0120]; using [0157]: in region II device active regions AR21; second source/drain contact CA2; [0161]) on a second one of the source/drain regions ([0157]-[0158]: 260); and
forming a second dielectric through-silicon via ([0111] and [0171]: 294) extending through the substrate,
the second dielectric through-silicon via (294) having a front-side surface in contact with the second source/drain contact (Fig. 7; CA2).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1) as applied above and further in view of Shin et al. (US 2022/0238433 A1).
Regarding claim 21: Oh and Yoshida teach the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof.
Oh does not expressly teach that the first dielectric through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof.
Shin teaches (e.g., Figs. 1-2) a method comprising forming a first dielectric through-silicon via ([0029]: 235) made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof ([0029]: aluminum nitride (AlN)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh as modified by Nishio, the method of forming a first dielectric through-silicon via made of aluminum nitride, as taught by Shin, for the benefits of increasing adhesion between the conductive layers and the insulating layer to improve reliability of the semiconductor device (Shin: [0029]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied or combination of references in the prior rejection of record for any teaching or matter specifically challenged in the argument or of the newly added limitations.
Applicant's arguments filed 06/16/2026 have been fully considered but they are not persuasive.
Applicant argued that the Oh, Nishio, Kim331, Yoshida and Shin does not render obvious limitations of claims 1-2, 7-8 and 10 because Oh does not show the step corresponding to etching process; "etching the substrate to form a through-silicon via opening" and "filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via."
However, the teaching of Oh can be said to be inherent or at least renders obvious the limitation, since no through-silicon via can be formed without etching the deposited layers followed by filling up the etched layers; Examiner out of a consideration to make the record clear, has provided secondary references to show that such as limitation is not patentable because not novel, based on the references provided,
In response to applicant's argument that the combination of the references would render the device inoperable, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Allowable Subject Matter
Claims 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 24: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method, comprising:
“wherein the dielectric material remains in the through-silicon via opening after the back-side interconnect structure is formed, wherein the back-side interconnect structure comprises a conductive feature, and wherein the first dielectric through-silicon via has a back-side surface formed by the dielectric material and in direct contact with the conductive feature”.
Regarding claim 25: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method, comprising:
“wherein a front-side surface of the first dielectric through-silicon via is at a level higher than the front-side surface of the metal through-silicon via”.
Claims 11-14, 22-23 and 26 are allowable.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method, comprising:
“wherein the dielectric through-silicon via is in direct contact with the source/drain contact, and a top surface of the dielectric through-silicon via is level with a top surface of the source/drain region; and forming a redistribution layer over the back-side of the substrate”.
Claims 12-14, 22 and 26 depend from claim 11, and therefore, are allowable for the same reason as claim 11.
Regarding claim 16: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method, comprising:
“wherein a bottommost portion of the dielectric TSV is in direct contact with the dielectric lateral structure and is laterally spaced apart from the metal line, a front-side surface of the dielectric TSV is at a level higher than a front-side surface of the metal-containing TSV”.
Claims 17, 23 and 27 depend from claim 16, and therefore, are allowable for the same reason as claim 16.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
Prosecution Insights