Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2022/0384311 A1).
Regarding independent claim 16: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 3-4 and 19-30 for description of device shown in Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a semiconductor structure, comprising:
a first semiconductor substrate ([0028]: 100);
a first interconnect structure ([0027]: FS) over a front-side of the first semiconductor substrate;
a second interconnect structure ([0094]: BS) over a back-side of the first semiconductor substrate;
a metal-containing through-silicon via (TSV) ([0111]: 192) extending though the first semiconductor substrate and electrically coupled to the first (FS) and second interconnect structures (BS); and
a dielectric TSV ([0111]: 194) extending through the first semiconductor substrate, the dielectric TSV being made of a material having a thermal conductivity greater than about 150 W/m/K ([0015]-[0018] and [0025]: Figs. 2-5 are cross-sections of Fig. 1; [0111]: silicon oxycarbonitride (SiOCN); as used in the specification [0017] the term “about” is considered within 20%; this meets the claim limitation).
wherein the second interconnect structure comprises a dielectric layer ([0122]: 321 in region AR11), a metal line ([0122]: BM1 in region AR11) laterally extending in the dielectric layer, and
a dielectric lateral structure (Fig. 7; [0122]: adjacent dielectric in region AR12) disposed in the dielectric layer, and
wherein a bottommost portion of the dielectric TSV (192) is in direct contact with the dielectric lateral structure (Fig. 7; [0122]: adjacent dielectric in region AR12) and is laterally spaced apart from the metal line (BM1).
Regarding claim 17: Oh teaches the claim, limitation of the semiconductor structure of claim 16, on which this claim depends, further comprising:
a semiconductor device ([0155]-[0156]: TR1 with active regions A11, A12 or TR2 with active regions A21, A22) on the front-side of the first semiconductor substrate,
the semiconductor device comprising a channel region ([0157]-[0160]: region between source/drain regions 160),
a gate structure ([0157]: G1) extending across the channel region, and
source/drain regions ([0157]-[0158]: 160) on the channel region and at opposite sides of the gate structure (G1); and
a source/drain contact ([0159]-[0160]: CA1) on one of the source/drain regions,
wherein the dielectric TSV (194) has a front-side surface in contact with the source/drain contact (CA1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Nishio et al. (US 2010/0283130 A1).
Regarding independent claim 1: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 19-30 for the manufacturing steps for making device of Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a method, comprising:
forming a semiconductor device ([0155]-[0156]: TR1 with active regions A11, A12 or TR2 with active regions A21, A22) over a front-side of a substrate ([0155]-[0156]: 100), the semiconductor device comprising:
a channel region ([0157]-[0160]: region between source/drain regions 160),
a gate structure ([0157]: G1) across the channel region, and
source/drain regions ([0157]-[0158]: 160) on the channel region and at opposite sides of the gate structure (G1);
forming a first source/drain contact ([0159]-[0160]: CA1) on a first one of the source/drain regions;
forming a front-side interconnect structure ([0163]: FV1/FM1) over the first source/drain contact;
forming a first dielectric through-silicon via ([0169]-[0171]: TV1) extending through the substrate from a cross-sectional view (FIG. 28),
the first dielectric through-silicon via (TV1) overlapping the first source/drain contact (CA1) from a top view (FIG. 28; [0160]); and
forming a back-side interconnect structure ([0173]: BM1) over a back-side of the substrate (100),
wherein the first dielectric through-silicon via (TV1) has a back-side surface in contact with the back-side interconnect structure (BM1).
Oh does not expressly teach
etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via.
Nishio teaches (e.g., Figs. 1A-4C) a method, comprising forming a substrate ([0054]: 1);
Nishio further teaches etching the substrate ([0060]: 1) to form a through-silicon via opening ([0060]: 14);
filling an entirety of the through-silicon via opening with a dielectric material ([0061]: 15) to form a first dielectric through-silicon via ([0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via, as taught by Nisio, for the benefits of reducing or eliminating interconnect material that can cause defects, when forming internal interconnects of the semiconductor device above the through holes 14 in a later step (Nishio: [0062]).
Regarding independent claim 11: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 19-30 for the manufacturing steps for making device of Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a method, comprising:
forming a channel region ([0157]-[0158]: region between source/drain 160) over a front-side of a substrate;
forming a source/drain region ([0157]-[0158]: region between source/drain 160) over a sidewall of the channel region (source/drain regions of FinFETs are inherently adjacent the channel region);
forming a source/drain contact ([0159]-[0160]: CA1) over the source/drain region;
forming an interconnect structure ([0164]: FM1/FV1) over a front-side of a substrate ([0163] and [0174]: 100) the source/drain contact (CA1);
etching the substrate from a back-side of the substrate ([0167]-[0173]) to form a through-silicon via opening ([0167]-[0173]: through-silicon via opening is formed to reach exposed interconnect structure FM1/FV1) until the interconnect structure is exposed;
forming a dielectric through-silicon via ([0111]: silicon dioxide SiO.sub.2) in the through-silicon via opening;
wherein the dielectric through-silicon via is in direct contact with the source/drain contact; and
forming a redistribution layer ([0174]-[0175]) over the back-side of the substrate.
Oh does not expressly teach that
etching the substrate until the source/drain contact is exposed;
wherein the dielectric through-silicon via is in direct contact with the source/drain contact.
Oh does not teach expressly teach that the first dielectric through-silicon via has a front-side surface in direct contact with the first source/drain contact.
Nishio teaches (e.g., Figs. 1A-4C) a method, comprising a substrate (Fig. 3B; [0067]: substrate 1) and a source/drain contact ([0063]: 7/8a);
Nishio further teaches etching the substrate (Fig. 3B; [0067]: substrate 1) until the source/drain contact is exposed ([0063]: 7/8a);
forming a first dielectric through-silicon via ([0069]: 12/13) having a front-side surface in direct contact with the first source/drain contact ([0063]: 7/8a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate until the source/drain contact is exposed; wherein the dielectric through-silicon via is in direct contact with the source/drain contact, as taught by Nishio, for the benefits of protecting the interconnect interface between the through-via and the source/drain contact, thus avoiding contact oxidation, which in turn will reduce signal delays of the device in operation.
Regarding claim 13: Oh teaches the claim, limitation of the method of claim 11, on which this claim depends,
wherein the redistribution layer comprises a dielectric layer ([0094]: 321) and a metal line ([0173]: BM1) laterally extending in the dielectric layer, and
the dielectric through-silicon via ([0109]-[0111]: 194) is in contact with the metal line (BM1).
Regarding claim 14: Oh teaches the claim, limitation of the method of claim 11, on which this claim depends,
wherein the redistribution layer comprises a dielectric layer ([0177]: 321) and a dielectric lateral structure in the dielectric layer ([0177]: dielectric layer includes dielectric lateral structure), and the metal-free through-silicon via is in contact with the dielectric lateral structure (321).
Alternatively, should the limitation “filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via” to be interpreted as the through-silicon via comprised only of dielectric in its final step, then this limitation is taught below:
Claims 1, 2, 7-8, 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1).
Regarding independent claim 1: Oh teaches (e.g., Fig. 1 and Fig. 7; using Figs. 19-30 for the manufacturing steps for making device of Fig. 7; [0022] and [0154]-[0179]: a method for fabricating the semiconductor device) a method, comprising:
forming a semiconductor device ([0155]-[0156]: TR1 with active regions A11, A12 or TR2 with active regions A21, A22) over a front-side of a substrate ([0155]-[0156]: 100), the semiconductor device comprising:
a channel region ([0157]-[0160]: region between source/drain regions 160),
a gate structure ([0157]: G1) across the channel region, and
source/drain regions ([0157]-[0158]: 160) on the channel region and at opposite sides of the gate structure (G1);
forming a first source/drain contact ([0159]-[0160]: CA1) on a first one of the source/drain regions;
forming a front-side interconnect structure ([0163]: FV1/FM1) over the first source/drain contact;
forming a first dielectric through-silicon via ([0169]-[0171]: TV1) extending through the substrate from a cross-sectional view (FIG. 28),
the first dielectric through-silicon via (TV1) overlapping the first source/drain contact (CA1) from a top view (FIG. 28; [0160]); and
forming a back-side interconnect structure ([0173]: BM1) over a back-side of the substrate (100),
wherein the first dielectric through-silicon via (TV1) has a back-side surface in contact with the back-side interconnect structure (BM1).
Oh does not expressly teach
etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via.
Yoshida teaches (e.g., Fig. 4) a method comprising etching a substrate ([0064]-[0065]) to form a through-silicon via opening ([0064]-[0065]), filling an entirety of a through-silicon via opening with a dielectric material to form a first dielectric through-silicon via ([0065]: 176).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via, as taught by Yoshida, for the benefits of completely protecting the integrated circuit device from signal interference of adjacent devices and thus improving device resilience.
Regarding claim 2: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via is made of a material having a thermal conductivity greater than about 150 W/m/K ([0015]-[0018] and [0025]: Figs. 2-5 are cross-sections of Fig. 1; [0111]: silicon oxycarbonitride (SiOCN); as used in the specification [0017] the term “about” is considered within 20%; this meets the claim limitation).
Regarding claim 7: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the back-side interconnect structure comprises a dielectric layer ([0094]: 321) and a metal line laterally (Fig. 7; [0119]-[0120]: metal line BM1 laterally extending between the dielectric layer) extending in the dielectric layer (321), and
the back-side surface of the first dielectric through-silicon via (194) is in contact with the metal line (BM1).
Regarding claim 8: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the back-side interconnect structure ([0173]: BM1) comprises
a dielectric layer ([0094]: 321), a metal line laterally extending (Fig. 7; [0119]-[0120]: metal line BM1 laterally extending between the dielectric layer) in the dielectric layer (321), and
a dielectric lateral structure in the dielectric layer (Fig. 7; [0177]), and
the back-side surface of the first dielectric through-silicon via (194) is in contact with the dielectric lateral structure (321).
Regarding claim 10: Oh teaches the claim, limitation of the method of claim 8, on which this claim depends,
further comprising: forming a buried power rail ([0164]: PW11) on the front-side of the substrate (Fig. 7; [0170]: upper surface of substrate 100); and
forming a metal through-silicon via ([0171]: 192) extending through the substrate,
the metal through-silicon via (192) having a front-side surface in contact with the buried power rail (PW11), and a back-side surface in contact with the metal line (BM1) of the back-side interconnect structure.
Regarding claim 23: Oh teaches the claim, limitation of the semiconductor structure of claim 16, on which this claim depends.
Oh does not expressly teach that the dielectric TSV occupies an entire cross-sectional area of a through-silicon via opening within the first semiconductor substrate.
Yoshida teaches (e.g., Fig. 4) a semiconductor structure comprising a substrate ([0064]-[0065]) and a through-silicon via opening ([0064]-[0065]);
Yoshida further teaches that the dielectric TSV occupies an entire cross-sectional area of a through-silicon via opening within the first semiconductor substrate (Fig. 4; [0065]: 176).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the structure of Oh, the dielectric TSV occupying an entire cross-sectional area of the through-silicon via opening within the first semiconductor substrate, as taught by Yoshida, for the benefits of completely protecting the integrated circuit device from signal interference of adjacent devices and thus improving device resilience.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Nishio et al. (US 2010/0283130 A1) as applied above and further in view of Yoshida (US 2016/0211348 A1)
Regarding claim 22: Oh teaches the claim, limitation of the method of claim 11, on which this claim depends,
wherein forming the dielectric through-silicon via in the through-silicon via opening comprises:
filling an entirety of the through-silicon via opening with a dielectric material.
Yoshida teaches (e.g., Fig. 4) a method comprising etching a substrate ([0064]-[0065]) to form a through-silicon via opening ([0064]-[0065]),
filling an entirety of a through-silicon via opening with a dielectric material to form a dielectric ([0065]: 176).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method of etching the substrate to form a through-silicon via opening; filling an entirety of the through-silicon via opening with a dielectric material to form a first dielectric through-silicon via, as taught by Yoshida, for the benefits of completely protecting the integrated circuit device from signal interference of adjacent devices and thus improving device resilience.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1) as applied above and further in view of Nishio et al. (US 2010/0283130 A1).
Regarding claim 5: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via (194) has a front-side surface in contact with the first source/drain contact (160).
Oh as modified by Yoshida does not teach expressly teach that the first dielectric through-silicon via has a front-side surface in direct contact with the first source/drain contact.
Nishio teaches a first dielectric through-silicon via ([0069]: 12/13) having a front-side surface in direct contact with a first source/drain contact ([0063]: 7/8a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh, the method wherein the first dielectric through-silicon via has a front-side surface in direct contact with the first source/drain contact, as taught by Nishio, for the benefits of reducing signal delays of the device in operation.
Regarding claim 6: Oh teaches the claim, limitation of the method of claim 5, on which this claim depends, further comprising:
forming a second source/drain contact (Fig. 7; [0119]-[0120]; using [0157]: in region II device active regions AR21; second source/drain contact CA2; [0161]) on a second one of the source/drain regions ([0157]-[0158]: 260); and
forming a second dielectric through-silicon via ([0111] and [0171]: 294) extending through the substrate,
the second dielectric through-silicon via (294) having a front-side surface in contact with the second source/drain contact (Fig. 7; CA2).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Nishio et al. (US 2010/0283130 A1) as applied above and further in view of Shin et al. (US 2022/0238433 A1).
Regarding claim 12: Oh teaches the claim, limitation of the method of claim 11, on which this claim depends,
wherein the dielectric through-silicon via comprises an oxide or a nitride, chemical vapor deposition diamond, or combinations thereof ([0109]-[0111]: 194).
Oh does not expressly teach that the dielectric through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof.
Shin teaches (e.g., Figs. 1-2) a method comprising forming a dielectric through-silicon via ([0029]: 235) made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof ([0029]: aluminum nitride (AlN)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh as modified by Nishio, the method of forming a dielectric through-silicon via made of aluminum nitride, as taught by Shin, for the benefits of increasing adhesion between the conductive layers and the insulating layer to improve reliability of the semiconductor device (Shin: [0029]).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) Yoshida US 2016/0211348 A1) as applied above and further in view of Kim et al., Hereinafter Kim722 (US 2021/0375722 A1).
Regarding claim 3: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
Oh as modified by Yoshida does not expressly teach that the first dielectric through-silicon via is made of metal oxide.
However, Kim teaches (e.g., Figs. 2-4) a method comprising a first dielectric through-silicon via ([0035] and [0059]);
Kim722 further teaches that the first dielectric through-silicon via is made of metal oxide ([0035] and [0059]: Al2O3, Aluminum Oxide).
It is noted that metal oxide material is a suitable material for a dielectric through-silicon via.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.) MPEP 2141.07.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to select a first dielectric through-silicon via made of metal oxide, as taught by Kim722, for its intended use; in addition, metal oxide dielectrics have a higher thermal conductivity, which can help transfer heat away from the device, and thus improve device reliability.
Regarding claim 4: Oh teaches the claim, limitation of the method of claim 1, on which this claim depends,
Oh does not expressly teach that the first dielectric through-silicon via is made of metal nitride.
However, Kim teaches (e.g., Fig. 2) a method comprising a first dielectric through-silicon via ([0035] and [0059]);
Kim further teaches that the first dielectric through-silicon via is made of metal nitride ([0035] and [0059]: AlN, Aluminum nitride).
It is noted that metal nitride material is a suitable material for a dielectric through-silicon via.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.) MPEP 2141.07.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to select a first dielectric through-silicon via made of metal oxide, a taught by Kim722, for its intended use; in addition, metal nitride dielectrics have a higher thermal conductivity, which can help transfer heat away from the device, and thus improving device reliability.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Nishio et al. (US 2010/0283130 A1) as applied above and further in view of Kim et al., Hereinafter, Kim331 (US 2020/0373331 A1).
Regarding claim 9: Oh teaches the claim, limitation of the method of claim 8, on which this claim depends,
Oh, does not expressly teach that the dielectric lateral structure is made of a same material as the first dielectric through-silicon via.
However, Oh teaches that the first dielectric through-silicon via comprises
silicon oxycarbonitride (SiOCN) ([0111]).
Kim331 teaches (e.g., Figs. 1A-1C and Fig. 2A-2C) a method comprising a dielectric lateral structure ([0042]: 105) comprising silicon oxynitride (SiON) ([0042]).
It is noted that silicon oxynitride, SiON is an art recognized material suitable for use as a dielectric lateral structure.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.) MPEP 2141.07.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to select a material such that the dielectric lateral structure is made of a same material as the first dielectric through-silicon via, as taught by Oh as modified by Kim331 because on ordinary skill in the art would be motivated to use the same dielectric material whenever possible to reduce the latency in manufacturing, and thus speed up manufacturing throughput.
Regarding claim 15: Oh teaches the claim, limitation of the method of claim 14, on which this claim depends,
Oh, does not expressly teach that the dielectric lateral structure is made of a same material as the metal-free through-silicon via.
However, Oh teaches that the first dielectric through-silicon via comprises
silicon oxycarbonitride (SiOCN) ([0111]).
Kim331 teaches (e.g., Figs. 1A-1C and Fig. 2A-2C) a method comprising a dielectric lateral structure ([0042]: 105) comprising silicon oxynitride (SiON) ([0042]).
It is noted that silicon oxynitride, SiON is an art recognized material suitable for use as a dielectric lateral structure.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.) MPEP 2141.07.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to select a material such that the dielectric lateral structure is made of a same material as the metal-free through-silicon via, as taught by Oh as modified by Kim331 because on ordinary skill in the art would be motivated to use the same dielectric material whenever possible to reduce the latency in manufacturing, and thus speed up manufacturing throughput.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Yoshida (US 2016/0211348 A1) as applied above and further in view of Shin et al. (US 2022/0238433 A1).
Regarding claim 21: Oh and Yoshida teach the claim, limitation of the method of claim 1, on which this claim depends,
wherein the first dielectric through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof.
Oh does not expressly teach that the first dielectric through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof.
Shin teaches (e.g., Figs. 1-2) a method comprising forming a first dielectric through-silicon via ([0029]: 235) made of beryllium oxide, aluminum nitride, chemical vapor deposition diamond, or combinations thereof ([0029]: aluminum nitride (AlN)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Oh as modified by Nishio, the method of forming a first dielectric through-silicon via made of aluminum nitride, as taught by Shin, for the benefits of increasing adhesion between the conductive layers and the insulating layer to improve reliability of the semiconductor device (Shin: [0029]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied or combination of references in the prior rejection of record for any teaching or matter specifically challenged in the argument or of the newly added limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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