DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been received / retrieved and recorded.
Claim Objections
Claim 4 is objected to because of the following informalities:
Regarding claim 4, “PI” used first time in the claim should be fully spelled. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-7 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Hu (CN110545625A).
Regarding claim 1, Hu, figure 11, discloses a flexible printed circuit comprising: an intermediate layer (layer 11 with circuit layer on top and bottom of the surface) and two protective layers (upper part of layer 30 and layer 31, on the upper and lower side) wrapped on opposite sides of the intermediate layer, the intermediate layer comprising a substrate layer (11) in the middle, the substrate layer having a through hole (though hole of conductive section 14), wherein the intermediate layer further comprises a first line layer and a second line layer respectively provided on opposite sides of the substrate layer (circuit layer 20, on both the sides) a first overlay layer (the other part or layer 30) and a second overlay layer (the other part of layer 30) respectively provided on opposite sides of the substrate layer and a guide member (conductive section 14) embedded in the through hole and connecting the first and second line layers (see figure), the first line layer being embedded in the first overlay layer and the second line layer being embedded in the second overlay layer (see figure).
Regarding claim 2, Hu further discloses wherein the surfaces of the first line layer and the first overlay layer are flush on the side away from the substrate layer, and the surfaces of the second line layer and the second overlay layer are flush on the side away from the substrate layer (see figure).
Regarding claim 3, Hu further discloses wherein the protective layer comprises a adhesive layer (30) attached to the outer side of the intermediate layer, and an insulating layer (31) located on the side of the adhesive layer away from the intermediate layer.
Regarding claim 4, Hu further discloses wherein both the substrate layer and the insulating layer are PI materials (see description, figure 1-4).
Regarding claim 6, Hu further discloses wherein the first line layer, the second line layer and the guide member are made of copper (see description of figure 1).
Regarding claim 7, Hu discloses the structure. The recitation the first line layer and the second line layer are prepared by means of PI metallization, copper plating and copper reduction on opposite sides of the substrate layer in turn, are process limitation in a product claim. Such process limitations defines the claimed invention over the prior art to the degree that it defines the product itself. A process limitation cannot serve to patentably distinguish the product over the prior art, in the case that the product is same as, or obvious over the prior art. See Product-by-Process in MPEP § 2113 and 2173.05(p) and In re Thorpe, 777 F.2d 695, 227 USPQ 964, 966 (Fed. Cir. 1985).
Therefore, Hu meets the limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu, as applied to claim 1 above, and further in view of Kim (US 2022/0304147), and Funaya (US 2009/0046441).
Regarding claim 4, Hu does not disclose wherein the first overlay layer and the second overlay layer are light-sensitive overlay films.
Kim, figure 2, discloses a circuit board with the insulating layers formed of light-sensitive (photo sensitive layer, 120, paragraph 0111), reliably forming the cavity (paragraph 0012, 0050).
Funaya, 8 and 9, discloses a circuit board with a light-sensitive (photo-sensitive resin, including forming via / opening (paragraph 0172. 0176).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the board of Hu with the first overlay layer and the second overlay layer are light-sensitive overlay films, as taught by Kim, and Funaya, in order to have controlled openings for forming via / circuits.
Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Echigo (6,274,821), figure 1, discloses a circuit board with a substrate (L2i), a through hole in the substrate (via in the substrate, see figure, a first line pattern, a second line pattern (traces on the substrate), and overlay on the top and bottom (L2R and L3R).
Higashitani (2010/0224395), figure 5A-5I, discloses a circuit board formed with insulating substrate including a film and an adhesive (paragraph 0168).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISHWARBHAI B PATEL whose telephone number is (571)272-1933. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at 571 272 2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ISHWARBHAI B PATEL/Primary Examiner, Art Unit 2847
IBP / April 27, 2025